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arxiv: 2605.19590 · v1 · pith:BUEUYKLRnew · submitted 2026-05-19 · 🪐 quant-ph · physics.app-ph

Photolithography-Only Fabrication of Transmons Using Double-Oblique Evaporation

K. Aoyanagi , S. Abe , S. Chen , T. Inada , C. Kawai , Y. Mino , K. Nakamura , K. Nakazono
show 2 more authors
T. Nitta K. Watanabe
This is my paper

Pith reviewed 2026-05-20 05:29 UTC · model grok-4.3

classification 🪐 quant-ph physics.app-ph
keywords transmonJosephson junctionphotolithographyfabricationsuperconducting qubitshadow evaporationquantum device
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The pith

Double-oblique evaporation produces functional transmon qubits using only photolithography.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper shows that Josephson junctions for transmon qubits can be made without electron-beam lithography by relying on a bilayer resist and aluminum shadow evaporation in a modified double-oblique geometry. This creates crossing regions with areas near 10,000 square nanometers, which fall in the useful range for qubit design. Room-temperature resistance measurements confirm that the junctions land in the target resistance window and vary with design parameters. When these junctions are placed in complete transmon devices and cooled to 20 millikelvin inside a three-dimensional aluminum cavity, the devices display standard qubit behavior including a 4.865 GHz transition frequency, roughly 9 microseconds of energy relaxation, and 0.4 microseconds of coherence. The work establishes that a fully optical-lithography route can deliver operating superconducting qubits.

Core claim

A photolithography-only process using double-oblique evaporation fabricates Josephson junctions whose geometrical area reaches 10^4 nm² and whose room-temperature resistance matches transmon targets; when integrated into devices these junctions produce observable qubit operation at f01 = 4.865 GHz with T1 ∼ 9 μs and T2* ∼ 0.4 μs at 20 mK.

What carries the argument

Modified double-oblique evaporation geometry that uses shadow masking in a bilayer resist stack to narrow the aluminum electrode crossing region to qubit-relevant dimensions.

If this is right

  • Resistance can be tuned across a usable process window simply by changing the lithographic design.
  • Complete transmon devices can be built and operated without any electron-beam lithography step.
  • Basic qubit performance metrics are obtained in a standard three-dimensional cavity readout setup.
  • Junctions passing optical inspection and resistance screening can be selected for cryogenic testing.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The method may lower the barrier to fabricating larger numbers of qubits by removing the need for slow electron-beam writing.
  • Further process tuning could be tested to increase the observed relaxation and coherence times.
  • Combining this junction step with other photolithographic layers could support fully optical-lithography quantum circuits.

Load-bearing premise

Room-temperature resistance values and optical or SEM images of the junction area reliably indicate how the device will behave at millikelvin temperatures and what coherence times it will achieve.

What would settle it

Fabricated devices that pass room-temperature resistance screening and show the expected junction area under SEM nevertheless fail to exhibit a clear qubit spectrum or show energy relaxation times below 1 microsecond when measured at 20 mK.

Figures

Figures reproduced from arXiv: 2605.19590 by C. Kawai, K. Aoyanagi, K. Nakamura, K. Nakazono, K. Watanabe, S. Abe, S. Chen, T. Inada, T. Nitta, Y. Mino.

Figure 1
Figure 1. Figure 1: FIG. 1. Schematic illustration of the double-oblique evapora [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: FIG. 2. Optical and SEM images of the fabricated double [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3. Room-temperature resistance as a function of de [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: FIG. 4. Low-temperature characterization of the fabricated [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗
read the original abstract

We investigate a photolithography-only fabrication process for transmon Josephson junctions using a modified double-oblique evaporation geometry. Using a bilayer resist process and Al shadow evaporation, we fabricate junction structures and confirm by optical and scanning electron microscopy that the resulting narrowed crossing region reaches a geometrical area on the order of $10^4~\mathrm{nm}^2$, which lies in the size range relevant to qubit junction fabrication. Room-temperature resistance screening shows that the junction resistance falls within the target range for the present transmon design over a usable process window and exhibits a clear design dependence. We further implement fabricated junctions in transmon devices and evaluate them in a three-dimensional Al cavity at $20 \, \mathrm{mK}$, where we observe basic transmon qubit operation with $f_{01}$=4.865 GHz, $T_1 \sim 9 \, \mu \mathrm{s}$, and $T_2^* \sim 0.4 \, \mu \mathrm{s}$. These results demonstrate the feasibility of realizing functional transmon devices in a photolithography-only process using double-oblique evaporation.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript presents a photolithography-only process for fabricating transmon Josephson junctions via a modified double-oblique Al shadow evaporation using bilayer resist. Optical and SEM imaging confirm junction areas of order 10^4 nm². Room-temperature resistance screening indicates values fall in the target range for the transmon design, with clear dependence on design parameters over a usable process window. Fabricated junctions are integrated into transmon devices and tested in a 3D Al cavity at 20 mK, yielding basic qubit operation with f01 = 4.865 GHz, T1 ∼ 9 μs, and T2* ∼ 0.4 μs. The central claim is that these results demonstrate the feasibility of realizing functional transmon devices without electron-beam lithography.

Significance. If the results hold, the work could meaningfully simplify transmon fabrication workflows by removing reliance on e-beam lithography, potentially improving throughput and accessibility. A key strength is the direct experimental demonstration of a working device at millikelvin temperatures using the proposed process, resting on concrete measurements rather than parameter fits or circular derivations.

major comments (2)
  1. [transmon device evaluation] In the section on transmon device evaluation and cryogenic testing, basic qubit operation is reported for a single device (f01=4.865 GHz, T1 ∼9 μs, T2* ∼0.4 μs) without statistics from multiple devices, yield data, error bars, or controls. This is load-bearing for the feasibility claim, as it leaves open whether the observed performance is representative of the process window established by room-temperature screening or an outlier.
  2. [room-temperature resistance screening] In the room-temperature resistance screening results, the claim that resistance falls within the target range over a usable process window with design dependence is presented without quantitative variation statistics, number of devices tested, or explicit correlation analysis to low-temperature coherence metrics. This assumption underpins the validation of the photolithography-only process prior to cryogenic testing.
minor comments (2)
  1. [abstract and results] The approximate symbols (∼) for T1 and T2* in the abstract and results should be clarified to indicate whether they refer to the specific reported device or to typical/average values across devices.
  2. [fabrication process] A table summarizing key fabrication parameters (evaporation angles, rates, resist details) alongside measured room-temperature resistances would improve clarity and allow readers to assess the process window more quantitatively.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for their positive evaluation of the work's significance and for the constructive major comments. We address each point below, clarifying the scope of the current demonstration while incorporating revisions to improve transparency.

read point-by-point responses

  1. Referee: [transmon device evaluation] In the section on transmon device evaluation and cryogenic testing, basic qubit operation is reported for a single device (f01=4.865 GHz, T1 ∼9 μs, T2* ∼0.4 μs) without statistics from multiple devices, yield data, error bars, or controls. This is load-bearing for the feasibility claim, as it leaves open whether the observed performance is representative of the process window established by room-temperature screening or an outlier.

    Authors: We agree that statistics from multiple devices would strengthen claims of process reliability. The present manuscript is a proof-of-principle demonstration that functional transmons can be realized with the photolithography-only double-oblique process; the reported device was fabricated within the parameter window validated at room temperature and exhibited the design frequency. In the revised manuscript we have added explicit language stating that the cryogenic data represent a single-device demonstration, included measurement uncertainty estimates, and noted that comprehensive yield and multi-device statistics are planned for future work. revision: partial

  2. Referee: [room-temperature resistance screening] In the room-temperature resistance screening results, the claim that resistance falls within the target range over a usable process window with design dependence is presented without quantitative variation statistics, number of devices tested, or explicit correlation analysis to low-temperature coherence metrics. This assumption underpins the validation of the photolithography-only process prior to cryogenic testing.

    Authors: We accept that quantitative details on variation and sample count would improve clarity. The screening was performed across multiple test structures with systematically varied design parameters, confirming that resistances lie in the target range with observable dependence on those parameters. In the revision we specify the approximate number of structures examined and add a short description of the observed spread. Direct statistical correlation between room-temperature resistance and low-temperature coherence times is not yet available, as cryogenic measurements were performed on one representative device; the successful observation of the expected qubit frequency nevertheless provides supporting validation of the screening method. revision: yes

Circularity Check

0 steps flagged

No circularity: experimental fabrication report with direct measurements

full rationale

The manuscript describes a photolithography-based fabrication process for Josephson junctions, room-temperature resistance screening, SEM inspection of junction area, and low-temperature measurements of transmon devices in a 3D cavity. No derivation chain, fitted parameters renamed as predictions, self-citations used as uniqueness theorems, or ansatzes smuggled via prior work appear in the reported steps. All load-bearing claims reduce to direct experimental outcomes (resistance values in target range, observed f01, T1, T2*) rather than any equation or premise that is definitionally equivalent to its inputs. The work is therefore self-contained against external benchmarks with no circularity.

Axiom & Free-Parameter Ledger

1 free parameters · 1 axioms · 0 invented entities

The central claim rests on standard assumptions of superconducting thin-film deposition and resist lift-off processes; no new physical entities or fitted constants are introduced beyond routine process parameters.

free parameters (1)
  • evaporation angles and rates
    Chosen by the authors to produce the target junction overlap area; values are not stated numerically in the abstract.
axioms (1)
  • domain assumption Bilayer resist stack enables reliable shadow evaporation without shorting or excessive roughness
    Invoked implicitly when the authors state that the narrowed crossing region reaches the required geometrical area.

pith-pipeline@v0.9.0 · 5762 in / 1352 out tokens · 36645 ms · 2026-05-20T05:29:29.965663+00:00 · methodology

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Reference graph

Works this paper leans on

14 extracted references · 14 canonical work pages

  1. [1]

    J. Koch, T. M. Yu, J. Gambetta, A. A. Houck, D. I. Schuster, J. Majer, A. Blais, M. H. Devoret, S. M. Girvin, and R. J. Schoelkopf, Charge-insensitive qubit design de- rived from the cooper pair box, Physical Review A76, 042319 (2007)

    work page 2007

  2. [2]

    G. J. Dolan, Offset masks for lift-off photoprocessing, Ap- plied Physics Letters31, 337 (1977)

    work page 1977

  3. [3]

    Niemeyer and V

    J. Niemeyer and V. Kose, Observation of large dc super- currents at nonzero voltages in josephson tunnel junc- tions, Applied Physics Letters29, 380 (1976)

    work page 1976

  4. [4]

    Osman, J

    A. Osman, J. Simon, A. Bengtsson, S. Kosen, P. Krantz, D. P. Lozano, M. Scigliuzzo, P. Delsing, J. Bylander, and A. Fadavi Roudsari, Simplified josephson-junction fabrication process for reproducibly high-performance superconducting qubits, Applied Physics Letters118, 10.1063/5.0037093 (2021)

    work page doi:10.1063/5.0037093 2021

  5. [5]

    J. T. Monroe, D. Kowsari, K. Zheng, C. Gaikwad, J. Brewster, D. S. Wisbey, and K. W. Murch, Op- tical direct write of dolan–niemeyer-bridge junctions for transmon qubits, Applied Physics Letters119, 10.1063/5.0060246 (2021)

    work page doi:10.1063/5.0060246 2021

  6. [6]

    Foroozani, C

    N. Foroozani, C. Hobbs, C. C. Hung, S. Olson, D. Ash- worth, E. Holland, M. Malloy, P. Kearney, B. O’Brien, B. Bunday, D. DiPaola, W. Advocate, T. Murray, P. Hansen, S. Novak, S. Bennett, M. Rodgers, B. Baker- O’Neal, B. Sapp, E. Barth, J. Hedrick, R. Goldblatt, S. S. P. Rao, and K. D. Osborn, Development of transmon qubits solely from optical lithography...

    work page 2019

  7. [7]

    M. Bal, J. Long, R. Zhao, H. Wang, S. Park, C. R. H. McRae, T. Zhao, R. E. Lake, V. Monarkha, S. Sim- bierowicz, D. Frolov, R. Pilipenko, S. Zorzetti, A. Ro- manenko, C.-H. Liu, R. McDermott, and D. P. Pap- pas, Overlap junctions for superconducting quantum electronics and amplifiers, Applied Physics Letters118, 10.1063/5.0048621 (2021)

    work page doi:10.1063/5.0048621 2021

  8. [8]

    Van Damme, S

    J. Van Damme, S. Massar, R. Acharya, T. Ivanov, D. Perez Lozano, Y. Canvel, M. Demarets, D. Van- goidsenhoven, Y. Hermans, J. G. Lai, A. M. Vadiraj, M. Mongillo, D. Wan, J. De Boeck, A. Potoˇ cnik, and K. De Greve, Advanced cmos manufacturing of super- conducting qubits on 300 mm wafers, Nature634, 74–79 (2024)

    work page 2024

  9. [9]

    Potts, P

    A. Potts, P. Routley, G. Parker, J. Baumberg, and P. Groot, Novel fabrication methods for submicrometer josephson junction qubits, Journal of Materials Science Materials in Electronics12, 289 (2001)

    work page 2001

  10. [10]

    Lecocq, I

    F. Lecocq, I. M. Pop, Z. Peng, I. Matei, T. Crozes, T. Fournier, C. Naud, W. Guichard, and O. Buisson, Junction fabrication by shadow evaporation without a suspended bridge, Nanotechnology22, 315302 (2011)

    work page 2011

  11. [11]

    Muthusubramanian, M

    N. Muthusubramanian, M. Finkel, P. Duivestein, C. Zachariadis, S. L. M. van der Meer, H. M. Veen, M. W. Beekman, T. Stavenga, A. Bruno, and L. Di- Carlo, Wafer-scale uniformity of dolan-bridge and bridge- less manhattan-style josephson junctions for supercon- ducting quantum processors, Quantum Science and Tech- nology9, 025006 (2024)

    work page 2024

  12. [12]

    Ambegaokar and A

    V. Ambegaokar and A. Baratoff, Tunneling between su- perconductors, Phys. Rev. Lett.10, 486 (1963)

    work page 1963

  13. [13]

    H. Paik, D. I. Schuster, L. S. Bishop, G. Kirchmair, G. Catelani, A. P. Sears, B. R. Johnson, M. J. Reagor, L. Frunzio, L. I. Glazman, S. M. Girvin, M. H. De- voret, and R. J. Schoelkopf, Observation of high coher- ence in josephson junction qubits measured in a three- dimensional circuit qed architecture, Phys. Rev. Lett. 107, 240501 (2011)

    work page 2011

  14. [14]

    Dunsworth, A

    A. Dunsworth, A. Megrant, C. Quintana, Z. Chen, R. Barends, B. Burkett, B. Foxen, Y. Chen, B. Chiaro, A. Fowler, R. Graff, E. Jeffrey, J. Kelly, E. Lucero, J. Y. Mutus, M. Neeley, C. Neill, P. Roushan, D. Sank, A. Vainsencher, J. Wenner, T. C. White, and J. M. Mar- tinis, Characterization and reduction of capacitive loss induced by sub-micron josephson ju...

    work page 2017