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arxiv: 2606.03500 · v2 · pith:3GTBC5DXnew · submitted 2026-06-02 · 🪐 quant-ph · physics.ins-det

FPGA Based Feedforward System for Photonic Quantum Computing Applications

Daniel Duggan , Simon Filgis , Axel B. Bregnsbo , J\"urgen Saalm\"uller , Jonas S. Neergaard-Nielsen , Tobias Wintermantel , Ulrik L. Andersen This is my paper

Pith reviewed 2026-06-28 09:34 UTC · model grok-4.3

classification 🪐 quant-ph physics.ins-det
keywords FPGAfeedforwardhomodyne detectorcontinuous variablemeasurement-based quantum information processingphotonic quantum computingreal-time signal processinglow latency
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The pith

FPGA-based system achieves 196 ns end-to-end latency for real-time feedforward in photonic quantum protocols.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents an FPGA-based fast feedforward system integrated with a fiber-based homodyne detector to handle signal acquisition, conditioning, and logic operations in real time. It targets continuous-variable measurement-based quantum information processing protocols that rely on adaptive measurements and displacements. Existing work often relies on post-processing, which prevents real-time use, so the system is built to meet the low-latency demands of these protocols. The reported performance includes 15 dB clearance at 1 GHz, quantum efficiency above 95 percent, and a total latency of 196 ns.

Core claim

Our system performs signal acquisition, conditioning, and logic operations in real-time, meeting the tight latency requirements of photonic quantum computing protocols. The detector exhibits a large clearance of 15 dB at 1 GHz with 4 mW linear oscillator and quantum efficiencies of >95% with a total system latency of 196 ns.

What carries the argument

FPGA-based fast feedforward system with a fully fibre-based homodyne detector that carries out real-time acquisition, conditioning, and logic for CV MB-QIP.

Load-bearing premise

The measured 196 ns latency is low enough to satisfy the timing constraints of the CV MB-QIP protocols without any demonstration of closed-loop operation inside an actual quantum protocol.

What would settle it

A direct measurement showing that the required latency for a target CV MB-QIP protocol is shorter than 196 ns, or a closed-loop test in which the 196 ns delay prevents successful protocol execution.

Figures

Figures reproduced from arXiv: 2606.03500 by Axel B. Bregnsbo, Daniel Duggan, Jonas S. Neergaard-Nielsen, J\"urgen Saalm\"uller, Simon Filgis, Tobias Wintermantel, Ulrik L. Andersen.

Figure 1
Figure 1. Figure 1: Standing wave inside a cavity with perfectly reflecting [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Wigner functions for vacuum, coherent (α = 2), squeezed vacuum, and single-photon states. The single-photon state is non-Gaussian and has a negative Wigner function. to the eigenvalues of the quadrature operators xˆ and pˆ in￾troduced in (13). The variable q is a relative displacement vector and represents a spatial shift of x, the midpoint. The term ⟨x + 1 2 q| ϱˆ|x − 1 2 q⟩ encodes the off-diagonal eleme… view at source ↗
Figure 3
Figure 3. Figure 3: Concept of a joint system in the Gaussian formalism. [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Wigner functions showing subsystem A before and after xˆ-measurement on subsystem B. Homodyne detection displaces A in phase space, requiring real-time correction. reveals partial information about mode A, updating our best estimate of its state and resulting in a conditional shift of its mean vector [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Overview of how a cluster state is generated, here using [PITH_FULL_IMAGE:figures/full_fig_p005_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Feedforward System architecture and data flow. [PITH_FULL_IMAGE:figures/full_fig_p006_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Clearance and noise equivalent power (NEP) of the [PITH_FULL_IMAGE:figures/full_fig_p007_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: The Ring Buffer can delay output from the DAC via a [PITH_FULL_IMAGE:figures/full_fig_p008_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Clock Plan. The onboard clock generator Si570 sends a [PITH_FULL_IMAGE:figures/full_fig_p008_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: O_trig_o is a 10 MHz signal used to synchronise the [PITH_FULL_IMAGE:figures/full_fig_p008_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: The Ring Buffer delays the output data driving the IM [PITH_FULL_IMAGE:figures/full_fig_p009_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Lock_meas_o is a configurable signal used to control [PITH_FULL_IMAGE:figures/full_fig_p009_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: PM-Gain Calibration. In the top figure PM-Gain is set to 1, such that it has no affect. It is seen that for a −π to π (0-0.48 V) ramp output from the DAC, the PM produces a modulation greater than 2π. With the correct value of PM￾Gain set (0.687), a 2π modulation is correctly achieved. In a phase modulator, this effect is used directly to control the phase of the light. To convert phase modulation into in… view at source ↗
Figure 14
Figure 14. Figure 14: Measurement of the maximum DAC output. 0.96 V [PITH_FULL_IMAGE:figures/full_fig_p011_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: Schematic of the PM Adjust entity. The CORDIC [PITH_FULL_IMAGE:figures/full_fig_p011_15.png] view at source ↗
Figure 16
Figure 16. Figure 16: Schematic of the FF-system verification set-up. [PITH_FULL_IMAGE:figures/full_fig_p012_16.png] view at source ↗
Figure 17
Figure 17. Figure 17: Understanding the system calibration test. A 10 kHz sine wave is input, with an [PITH_FULL_IMAGE:figures/full_fig_p013_17.png] view at source ↗
Figure 18
Figure 18. Figure 18: Vivado simulation (top) and experimental data (bottom) of the system verification test. It is seen that the phase output [PITH_FULL_IMAGE:figures/full_fig_p014_18.png] view at source ↗
Figure 19
Figure 19. Figure 19: Vivado simulation (top) and experimental data (bottom) of the system latency, measured to be 196 ns. [PITH_FULL_IMAGE:figures/full_fig_p015_19.png] view at source ↗
Figure 20
Figure 20. Figure 20: Schematic of the FF-system calculation as mathemat [PITH_FULL_IMAGE:figures/full_fig_p016_20.png] view at source ↗
Figure 23
Figure 23. Figure 23: Summary of resources used by the implemented [PITH_FULL_IMAGE:figures/full_fig_p017_23.png] view at source ↗
Figure 22
Figure 22. Figure 22: Calculation validation data over 250 µs. [PITH_FULL_IMAGE:figures/full_fig_p017_22.png] view at source ↗
Figure 27
Figure 27. Figure 27: The optical signals input to the FF-system via a HD [PITH_FULL_IMAGE:figures/full_fig_p018_27.png] view at source ↗
Figure 24
Figure 24. Figure 24: Screen shot of Vitis’ memory inspector output show [PITH_FULL_IMAGE:figures/full_fig_p018_24.png] view at source ↗
Figure 25
Figure 25. Figure 25: Screen shot of data inside the Ax-BRAM. Screenshot [PITH_FULL_IMAGE:figures/full_fig_p018_25.png] view at source ↗
Figure 28
Figure 28. Figure 28: The system outputs the correct voltages verify [PITH_FULL_IMAGE:figures/full_fig_p018_28.png] view at source ↗
read the original abstract

Field-programmable gate arrays provide a high-performance solution for real-time signal processing in emerging quantum and photonic technologies. We present an FPGA-based fast feedforward system, that incorporates a high quantum efficiency fully fibre based homodyne detector, to enable low-latency signal processing critical for continuous variables (CV) measurement-based quantum information processing (MB-QIP) protocols. CV MB-QIP typically relies on adaptive measurements and/or displacements via feedforward to achieve scalability and universality, but existing implementations typically handle these operations in post-processing, limiting real-time applicability. Our system performs signal acquisition, conditioning, and logic operations in real-time, meeting the tight latency requirements of photonic quantum computing protocols. The detector exhibits a large clearance of 15 dB at 1 GHz with 4 mW linear oscillator and quantum efficiencies of >95% with a total system latency of 196 ns. This work highlights the role of FPGAs in bridging the gap between theoretical models and physical implementations in photonics-based technologies

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 0 minor

Summary. The manuscript presents an FPGA-based feedforward system integrated with a high-quantum-efficiency fibre-based homodyne detector for real-time signal acquisition, conditioning, and logic operations in continuous-variable measurement-based quantum information processing (CV MB-QIP). It reports concrete hardware performance metrics: 15 dB clearance at 1 GHz with 4 mW local oscillator, quantum efficiency >95%, and end-to-end system latency of 196 ns, asserting that these meet the requirements for adaptive measurements and displacements in photonic quantum computing protocols.

Significance. If the reported latency and detector performance are shown to satisfy the timing constraints of specific CV MB-QIP protocols and demonstrated in closed-loop operation, the work would provide a practical hardware bridge between theoretical feedforward requirements and physical implementations, enabling real-time rather than post-processed adaptive operations.

major comments (2)
  1. [Abstract] Abstract: The central claim that the system 'meets the tight latency requirements of photonic quantum computing protocols' lacks any explicit comparison between the measured 196 ns end-to-end latency and the numerical timing bounds required by the cited CV MB-QIP protocols, nor does it include a closed-loop demonstration inside an actual quantum circuit. This assumption is load-bearing for the paper's primary assertion.
  2. [Abstract] Abstract: Concrete performance figures (196 ns latency, 15 dB clearance, >95% QE) are stated without reference to a methods section, error analysis, uncertainty quantification, or raw data, preventing verification that the numbers support the protocol-requirement claim.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for their constructive comments. We address each major comment below and indicate where revisions will be made to the manuscript.

read point-by-point responses

  1. Referee: [Abstract] Abstract: The central claim that the system 'meets the tight latency requirements of photonic quantum computing protocols' lacks any explicit comparison between the measured 196 ns end-to-end latency and the numerical timing bounds required by the cited CV MB-QIP protocols, nor does it include a closed-loop demonstration inside an actual quantum circuit. This assumption is load-bearing for the paper's primary assertion.

    Authors: We agree an explicit comparison strengthens the abstract. The full manuscript (Introduction and Results) cites specific CV MB-QIP protocols with timing bounds typically in the 200-1000 ns range for real-time adaptive operations; our 196 ns end-to-end latency falls at the lower end of these bounds. We will revise the abstract to include a concise comparison phrase. A closed-loop demonstration within a full quantum circuit is outside the scope of this hardware characterization paper, which reports system-level metrics rather than an integrated quantum experiment; the latency comparison alone supports the claim for the stated purpose. revision: partial

  2. Referee: [Abstract] Abstract: Concrete performance figures (196 ns latency, 15 dB clearance, >95% QE) are stated without reference to a methods section, error analysis, uncertainty quantification, or raw data, preventing verification that the numbers support the protocol-requirement claim.

    Authors: The abstract is a concise summary; the Methods section details the measurement procedures for latency, clearance (at 1 GHz with 4 mW LO), and quantum efficiency (>95%), including error analysis and uncertainty quantification. Raw datasets are provided in the supplementary information. We will revise the abstract to add a brief reference to the Methods section for these figures. revision: yes

Circularity Check

0 steps flagged

No circularity: paper reports direct hardware measurements without derivations or fitted predictions

full rationale

The manuscript presents an FPGA-based feedforward system and reports empirical measurements (15 dB clearance at 1 GHz, >95% QE, 196 ns latency) obtained from hardware characterization. No equations, parameter fitting, self-citations used as load-bearing uniqueness theorems, or ansatzes appear in the provided text. The central claim that the measured latency meets CV MB-QIP requirements is an engineering assertion resting on external protocol literature rather than any internal derivation that reduces to the paper's own inputs by construction. The work is therefore self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

No free parameters, axioms, or invented entities are introduced; the work is a hardware demonstration report.

pith-pipeline@v0.9.1-grok · 5733 in / 1109 out tokens · 30017 ms · 2026-06-28T09:34:00.059568+00:00 · methodology

discussion (0)

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Reference graph

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