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arxiv: 2606.28837 · v1 · pith:WP7K42QYnew · submitted 2026-06-27 · 📡 eess.SY · cs.SY· eess.SP

A Comprehensive Design Framework for Vertical Power Delivery in High-Performance Computing

Sriharini Krishnakumar , Yaroslav Popryho , Mingeun Choi , Ramin Rahimzadeh Khorasani , Madhavan Swaminathan , Satish Kumar , Inna Partin-Vaisband This is my paper

Pith reviewed 2026-06-30 09:00 UTC · model grok-4.3

classification 📡 eess.SY cs.SYeess.SP
keywords vertical power deliverydistributed VPDGaN power switcheshigh-performance computingpower efficiencyvoltage conversionanalytical modelsHPC systems
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The pith

A distributed vertical power delivery framework reaches 84% efficiency for 48V-to-1V conversion in HPC systems using only 54% of the area under the load.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper develops a complete design framework for vertical power delivery in high-performance computing that includes a distributed architecture, an optimization method, and analytical models for performance evaluation. Existing approaches fall below 70% end-to-end efficiency, losing substantial energy as heat before reaching the chip. The new framework explores multi-stage conversions from 48V down to 1V and demonstrates that the 48V-to-1V case can hit 84% efficiency while occupying just over half the space beneath the processor, with voltage drops staying under 3% in steady state. This matters because power delivery bottlenecks limit the performance and energy use of large-scale computing platforms, and a systematic way to design better solutions could unlock higher power densities without excessive losses.

Core claim

The central discovery is that the distributed vertical power delivery (DVPD) approach, leveraging substrate-embedded GaN power switches along with tailored inductor and capacitor arrays, combined with multi-stage conversion schemes and analytical modeling of losses and drops, enables system-wide efficiencies of 84% for direct 48V-to-1V delivery at 54% area occupation, scaling up to 87.6% at higher area use, with peak steady-state drops of 2.7% and transient drops of 9% without decoupling capacitors, making it suitable for 1-50 kW loads in wafer-scale HPC.

What carries the argument

The DVPD architecture consisting of distributed power stages with embedded GaN switches and unit inductor-capacitor arrays, supported by analytical models for steady-state voltage drops and power losses.

Load-bearing premise

The analytical models used to calculate voltage drops and power losses accurately represent the behavior of real devices and interconnects without needing calibration for manufacturing variations.

What would settle it

Fabricating a DVPD prototype for the 48V-to-1V case and measuring end-to-end efficiency below 80% or steady-state voltage drops above 3% would disprove the performance claims.

Figures

Figures reproduced from arXiv: 2606.28837 by Inna Partin-Vaisband, Madhavan Swaminathan, Mingeun Choi, Ramin Rahimzadeh Khorasani, Satish Kumar, Sriharini Krishnakumar, Yaroslav Popryho.

Figure 1
Figure 1. Figure 1: Power delivery approaches, (a) traditional lateral power [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Architecture A1, A2, A3 employ DVPD architecture with power transistors and passives embedded in-substrate below [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Proposed design optimization framework for DVPD systems. Design components are described in Section [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Interaction between the proposed DVPD electrical de [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Minimum switching frequency, f min sw , of DSCH VRs in a DVPD system delivering 1kW@1V load power to the functional system at a current density of 2 A/mm2 . demonstration vehicle to expose key concepts, dependencies, and design tradeoffs in DVPD. By applying the proposed framework to DSCH, findings related to operating frequency and VR sizing are derived, which generalize to other converter topologies. Spe… view at source ↗
Figure 6
Figure 6. Figure 6: Sizing factor, w opt sw, in a DVPD system delivering 1 kW load power. The figure illustrates the general trend that the sizing factor decreases with input voltage, with the crossover point indicating the voltage at which footprint constraints begin to limit switch sizing. required number of unit inductors, NL, independently of the per-VR current (see (2)). Once the per-VR current drops below the saturation… view at source ↗
Figure 7
Figure 7. Figure 7: Intra-VR routing geometry scaling with increasing [PITH_FULL_IMAGE:figures/full_fig_p007_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Per-layer VIC footprint across three voltage conversion [PITH_FULL_IMAGE:figures/full_fig_p007_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Sensitivity of VR power loss to embedded inductor [PITH_FULL_IMAGE:figures/full_fig_p009_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Representative DVPD VR-cell implementation used [PITH_FULL_IMAGE:figures/full_fig_p010_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: Total conversion loss and loss distribution in a DVPD [PITH_FULL_IMAGE:figures/full_fig_p010_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Optimized floorplan designed with the automated [PITH_FULL_IMAGE:figures/full_fig_p011_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: Spatial voltage drop across a 1-kW, 1-V load system: [PITH_FULL_IMAGE:figures/full_fig_p012_13.png] view at source ↗
Figure 14
Figure 14. Figure 14: End-to-end power loss across traditional and DVPD [PITH_FULL_IMAGE:figures/full_fig_p012_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: Percent of power loss in a DVPD system using [PITH_FULL_IMAGE:figures/full_fig_p013_15.png] view at source ↗
read the original abstract

Power delivery -- including high-to-low voltage conversion, complex power distribution across heterogeneously integrated chiplets, and efficient interconnect allocation -- remains a critical bottleneck in high-performance computing (HPC) systems. Existing vertical power delivery (VPD) solutions are estimated to achieve less than 70\% system-wide end-to-end power delivery efficiency, defined from platform input power to delivered on-chip load power, with substantial energy lost as heat before reaching on-chip point-of-loads (POLs). In the absence of systematic design methodologies, evaluating power quality, exploring architectural alternatives, and optimizing performance rely on computationally prohibitive simulations, resulting in suboptimal designs. This paper introduces an end-to-end scalable power delivery framework for HPC systems, including distributed VPD (DVPD) architecture, DVPD design optimization methodology, and analytical models. The framework leverages substrate-embedded GaN power switches together with arrays of unit inductors and capacitors tailored for HPC applications. Multi-stage power conversion schemes (48V-to-1V, 48V-to-24V-to-1V, and 48V-to-12V-to-1V) are explored, with system-wide voltage drops and power losses evaluated under steady-state conditions. Design specifications for passive and active devices are formulated to meet next-generation efficiency targets. For the 48V-to-1V case, the proposed DVPD approach achieves 84\% system-wide efficiency while occupying 54\% of the area beneath the load system, with efficiency increasing to 87.6\% at 75\% area utilization across a 1--50~kW load range. Furthermore, steady-state voltage drops peak at 2.7\% and transient drops at 9\% (without decoupling capacitors), demonstrating the viability of DVPD for future wafer-scale HPC platforms.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The paper introduces an end-to-end scalable framework for vertical power delivery in HPC systems consisting of a distributed VPD (DVPD) architecture using substrate-embedded GaN switches and arrays of unit inductors/capacitors, a design optimization methodology, and analytical models for multi-stage conversion (48V-to-1V, 48V-to-24V-to-1V, 48V-to-12V-to-1V). It evaluates system-wide voltage drops and power losses under steady-state conditions and reports that the 48V-to-1V DVPD case achieves 84% efficiency at 54% area utilization beneath the load (rising to 87.6% at 75% utilization) over 1-50 kW, with peak steady-state drops of 2.7% and transient drops of 9% (no decoupling caps).

Significance. If the analytical models prove accurate, the framework would supply a systematic, simulation-light methodology for exploring and optimizing VPD architectures that currently rely on computationally expensive full-system simulations, potentially enabling efficiencies above the <70% baseline cited for existing solutions.

major comments (2)
  1. [Abstract / Analytical Models] Abstract and analytical-models description: the headline results (84% system efficiency, 2.7% steady-state drop, 9% transient drop) are generated exclusively by the paper's analytical models of losses and voltage drops, yet no derivation steps, explicit equations, parameter-calibration procedure, or tolerance analysis are supplied, preventing assessment of whether the models correctly embed interconnect parasitics, GaN non-idealities, and inductor/capacitor losses across the full 1-50 kW range.
  2. [Analytical Models / Results] Validation of models: the manuscript reports no cross-check of the analytical predictions against SPICE-level netlists, electromagnetic extraction, or measured prototypes; any systematic omission in the models (e.g., unmodeled parasitic inductance or switch R_on variation) would directly scale into the claimed efficiency and area numbers, making the central performance claims unverifiable from the given material.
minor comments (2)
  1. [Abstract] The abstract states that 'design specifications for passive and active devices are formulated' but provides no concrete criteria or optimization constraints used to arrive at those specifications.
  2. [Results] The transient-drop figure of 9% is given without decoupling capacitors; the manuscript should clarify whether this is a worst-case bound or an operating-point value and how it was obtained from the steady-state models.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback. We address the two major comments on the analytical models below, agreeing that additional detail is warranted for verifiability.

read point-by-point responses

  1. Referee: [Abstract / Analytical Models] Abstract and analytical-models description: the headline results (84% system efficiency, 2.7% steady-state drop, 9% transient drop) are generated exclusively by the paper's analytical models of losses and voltage drops, yet no derivation steps, explicit equations, parameter-calibration procedure, or tolerance analysis are supplied, preventing assessment of whether the models correctly embed interconnect parasitics, GaN non-idealities, and inductor/capacitor losses across the full 1-50 kW range.

    Authors: We agree the models require more explicit documentation. The revised manuscript will add a dedicated subsection with derivation steps and explicit equations for multi-stage loss and voltage-drop calculations (including GaN R_on, switching losses, inductor ESR, capacitor ESR, and interconnect parasitics). We will also include the parameter-calibration procedure from datasheets and a tolerance/sensitivity analysis over the 1-50 kW range. revision: yes

  2. Referee: [Analytical Models / Results] Validation of models: the manuscript reports no cross-check of the analytical predictions against SPICE-level netlists, electromagnetic extraction, or measured prototypes; any systematic omission in the models (e.g., unmodeled parasitic inductance or switch R_on variation) would directly scale into the claimed efficiency and area numbers, making the central performance claims unverifiable from the given material.

    Authors: The manuscript currently presents results from the analytical models without direct SPICE cross-validation. We will add a new results subsection comparing analytical predictions to SPICE netlist simulations for representative operating points (e.g., 10 kW and 50 kW) to verify embedding of parasitics and device non-idealities. Full electromagnetic extraction and hardware prototypes lie outside the scope of this framework paper but will be noted as future work. revision: partial

Circularity Check

0 steps flagged

No circularity: efficiencies and drops are model outputs, not inputs by construction

full rationale

The paper presents an analytical modeling framework whose outputs (84% efficiency, 2.7% steady-state drop, etc.) are computed from device and interconnect parameters for the DVPD architecture. No equations, fitted parameters, or self-citations are shown that would make these quantities equivalent to their own inputs by definition. The derivation chain therefore remains self-contained against external benchmarks and does not reduce to any of the enumerated circular patterns.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

The abstract does not enumerate free parameters or axioms; the central results rest on unspecified analytical models whose internal assumptions (device parasitics, loss mechanisms, steady-state operation) are not detailed.

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