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REVIEW 5 major objections 5 minor 35 references

The paper claims that PDS1500, a 64-channel 1 GSa/s 14-bit waveform readout, passes every electronics requirement of the Jinping Neutrino Experiment as demonstrated on the JNE-1ton prototype.

Reviewed by Pith at T0; open to challenge. T0 means a machine referee read the full paper against a public rubric. the ladder, T0–T4 →

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2026-08-01 13:31 UTC pith:MQKIBKJ6

load-bearing objection A solid, workmanlike instrumentation paper — the PDS1500 system is real and mostly validated, but the uncharacterized splitter and missing measurement details for ENOB/SNR are genuine gaps that need a revision before I'd rely on the comparative numbers. the 5 major comments →

arxiv 2607.19066 v2 pith:MQKIBKJ6 submitted 2026-07-21 physics.ins-det hep-ex

The Research and Development of New Electronics System and its Testing on the JNE-1ton Prototype Detector

Haoyan Yang , Yuzi Yang , Yapeng Wang , Changxu Wei , Haoyang Fu , Haozhe Sun , Juntao Liu , Zhiyi Liu
show 5 more authors
Tao Xue Jianmin Li Yinong Liu Zhe Wang Shaomin Chen
This is my paper
classification physics.ins-det hep-ex
keywords neutrino detector readoutwaveform digitizationclock distributionzero-delay modebaseline noiseenergy thresholdliquid scintillator detectorPMT readout electronics
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper reports a purpose-built readout system, PDS1500, for the Jinping Neutrino Experiment's 3000-channel slow-liquid-scintillator detector. The central claim is that this single-crate 64-channel waveform digitizer satisfies every stated electronics requirement: 1 GSa/s sampling at 14 bits, a deterministic zero-delay clock that keeps all channels synchronized, no data loss in a 1000 ns acquisition window, baseline noise one-third that of the commercial system previously used, timing drift of 0.3 ns across power cycles, and a trigger threshold of 0.1 MeV. Validation came from bench tests and deployment on the upgraded JNE-1ton prototype, with direct comparison against a commercial digitizer on the same PMT signals. The result matters because reaching a 0.1 MeV threshold is what would open the detector to low-energy solar neutrinos from the pp chain and 7Be, and the modular design is claimed to scale to the full 3000-channel detector.

Core claim

On its own terms, the paper establishes that a newly designed electronics chain—eight 8-channel 14-bit 1 GSa/s digitizer boards, a trigger/timing board, a high-speed backplane, and a PCIe acquisition board in one crate—meets all JNE specifications. The decisive feature is the clock network: a 50 MHz reference is distributed in a star topology, and each digitizer uses a zero-delay-mode jitter cleaner so the 1 GHz ADC sampling clocks and the global trigger stay phase-locked across all channels. Tested on the JNE-1ton prototype, the PDS1500 recorded 1000 ns waveforms with no dead-time losses, showed baseline noise about one-third of the reference system after amplitude normalization, held chann

What carries the argument

The load-bearing object is the deterministic zero-delay clock distribution. A timing board distributes a 50 MHz reference over the backplane to eight digitizer boards; each board's LMK04832 jitter cleaner (a clock chip) operates in zero-delay mode, feeding its 250 MHz output back into the PLL so the derived 1 GHz ADC sampling clock locks to the same phase as the incoming reference. Because the global trigger is also distributed in equal-length star topology, every channel samples the same phase of the PMT waveform simultaneously, eliminating the ±1 sampling-clock-cycle ambiguity and the need for offline waveform cropping. This mechanism is what produces the 0.3 ns power-cycle drift, zero-dea

Load-bearing premise

The comparative measurements assume the PMT signal splitter sends identical waveforms to both systems; if the two split paths differ in gain, bandwidth, or phase, the baseline-noise and waveform-agreement comparisons could reflect the splitter rather than the new electronics.

What would settle it

Characterize the splitter independently—measure each output against the input with a fast pulse generator and a network analyzer—or repeat the comparison with the two systems fed directly from the same calibrated source without a splitter. If the splitter's outputs differ by more than the claimed one-third baseline-noise ratio, or if direct-fed A/B tests do not reproduce the 0.3 ns drift and 0.1 MeV threshold, the central claim fails.

Watch this falsifier — get emailed when new claim-graph text bears on it.

If this is right

  • The full 3000-channel JNE detector can be read out by 64 such crates with a two-stage optical network, at a total estimated power of about 7.5 kW.
  • A 0.1 MeV energy threshold makes pp-chain and 7Be solar-neutrino measurements accessible, since the previous setup's efficiency fell sharply below about 0.5 MeV.
  • No post-acquisition inter-board alignment or cropping is needed, simplifying offline processing and removing a source of systematic timing error in vertex reconstruction.
  • A trigger rate up to 50 kHz and 64 Gbps per-crate throughput are sufficient for the waveform-based, high-precision event reconstruction JNE plans.
  • Since the electronics contribution to energy resolution saturates by about 9 bits, the 14-bit readout's value is in waveform fidelity and threshold, not in improving the 1-ton prototype's energy resolution.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The splitter-based comparison is the paper's unexamined hinge; until the splitter's own bandwidth, impedance, and phase consistency are published, the factor-of-three noise advantage and waveform agreement should be treated as system-level results rather than pure electronics performance.
  • The zero-delay star-topology clock scheme is not specific to JNE; it could plausibly be adopted by other large liquid-scintillator or water-Cherenkov detectors that need sub-nanosecond multi-crate synchronization.
  • A testable extension is to verify whether the 0.3 ns PLL alignment step is deterministic per power cycle; if not, a continuous phase monitor or power-on alignment calibration would be needed for the full experiment's long-term stability.
  • The claim that 14-bit depth does not improve energy resolution is specific to this detector's light yield; in a higher-light-yield configuration, or for single-photon counting and Cherenkov/scintillation separation, the extra bits could matter more than the paper's saturation curve suggests.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

5 major / 5 minor

Summary. The paper reports the development and testing of PDS1500, a new 64-channel readout system for the Jinping Neutrino Experiment (JNE), offering 1 GSa/s sampling, 14-bit resolution, a 64 Gbps data path, and a deterministic clock distribution architecture. The system was deployed on the upgraded JNE-1ton prototype, and its performance was compared with the commercial CAEN V1751 digitizer using a two-way PMT signal splitter. The authors claim zero data loss in a 1000 ns window, baseline noise one-third of the CAEN level, 0.3 ns timing drift across power cycles, an energy threshold of 0.1 MeV, and consistent energy resolution at ~9%, concluding that the system fully satisfies JNE requirements and is scalable to 3000 channels.

Significance. If the reported figures are substantiated, PDS1500 represents a credible readout solution for a next-generation large liquid-scintillator neutrino detector. The paper contains direct comparative measurements for several key metrics, and the design choices (star-distributed clocks, high-throughput PCIe readout, low-noise front end) are well motivated. However, several load-bearing details are missing: the splitter used for all comparative measurements is not characterized, the ENOB/SNR specifications lack a measurement description, and the simulation supporting the detector-limited energy-resolution conclusion is undocumented. These gaps currently prevent the paper from fully supporting its central claim.

major comments (5)
  1. [Section 3.1, Figure 7] The comparative validation relies entirely on a two-way PMT signal splitter feeding the same pulses to the CAEN V1751 and PDS1500. The paper only states that the splitter 'ensures that the waveforms of the two output signals are consistent' and gives no measurement of its bandwidth, port-to-port gain match, return loss, or propagation-delay dispersion. All differential metrics—baseline noise ratio (Fig. 10), waveform χ²/NDF (Fig. 12), energy threshold (Fig. 17), and energy resolution (Fig. 19)—depend on the two split paths being identical. If the paths differ in attenuation or frequency response, the differences attributed to PDS1500 would be inseparable from splitter effects. Please provide splitter specifications and a standalone characterization, or alternatively use a measurement configuration that does not require an uncharacterized analog component.
  2. [Table 1, Section 3.3] Table 1 lists ENOB = 10.6 bit and SNR ≈ 65.6 dB with a caption stating these are 'derived from the actual measurement results presented in the following sections,' but no section presents an ENOB or SNR measurement. Without the measurement method (e.g., sine-wave curve fit, FFT-based SNR, input frequency, record length), these headline dynamic-performance numbers are unverifiable. The authors should add a measurement description and results, or clearly label the values as design estimates.
  3. [Sections 3.3.2 and 3.3.3, Eq. (1)] The normalization factor 0.04858 for PDS1500-to-CAEN amplitude conversion is calibrated from the peak-height ratio distribution (Fig. 9) using the same synchronous events that are subsequently used for the baseline-noise comparison (Fig. 10) and the waveform-fidelity χ² test (Eq. 1, Fig. 12). This couples the amplitude calibration to the performance comparison: any gain mismatch between the two split paths or between the two systems is absorbed into the factor, so the factor-of-three noise improvement and χ²/NDF ≈ 1 are not fully independent validations. An independent calibration source (e.g., a precision pulser) or a validation on a separate dataset should be provided.
  4. [Section 3.3.5, Figure 17] The energy-threshold comparison confounds the electronics system with the multichannel trigger threshold setting. The PDS1500 spectrum obtained with Tr_multi=10 is compared against spectra with Tr_multi=45 from both the CAEN system and the PDS1500 itself. The lower threshold attainable with PDS1500 is a genuine system-level advantage (the CAEN DAQ crashed when the threshold was lowered), but the 0.1 MeV versus 0.5 MeV comparison does not isolate the electronics from the trigger-setting change. Please either present a comparison at the same trigger threshold where possible, or clearly frame the result as a combined electronics-plus-DAQ threshold capability rather than a difference in electronics alone.
  5. [Section 3.3.6, Figure 19(b)] The simulation used to argue that energy resolution saturates near 9% beyond 9 bits and is therefore detector-limited is not described. Figure 19(b) shows curves with and without 'Baseline fluct. = 0.5 ADC bin', but the simulation parameters (light yield, PMT response, noise model, event selection, and how the 'intrinsic 9%' was set) are not given. Since the conclusion that 14-bit resolution provides no energy-resolution benefit rests on this simulation, the simulation setup must be documented, or the claim should be limited to the measured data.
minor comments (5)
  1. [Table 1] The tabular header contains a typo: 'PDS11500' should be 'PDS1500'.
  2. [Section 3.3.4] The sentence 'the PDS1500 system has a time drift of only 0.3 nslower than the experimental time step' is missing a space; should read '0.3 ns lower'.
  3. [Section 3.3.1] The 'zero data loss' claim is based on only two comparison runs. A more thorough statistical statement, including the expected loss rate over longer operation, would strengthen the claim.
  4. [Figure 9] The axis labels for the histogram and the top-row plots are unclear (e.g., '3 10×Entries' and '3 −10×Peak height ratio'). Please reformat to standard scientific notation.
  5. [Section 3.3.5] The single-channel threshold is described as 'approximately one single-photoelectron signal'; the conversion from CAEN ADC units to photoelectrons should be justified or referenced.

Circularity Check

0 steps flagged

No significant circularity: the reported metrics are direct comparisons against an external commercial digitizer; the one calibration constant (0.04858) does not force the headline results.

full rationale

The paper's central validation is an external benchmark against the commercial CAEN V1751 rather than against its own outputs. The only fitted quantity in the comparison chain is the 0.04858 normalization factor, obtained from the mean peak-height ratio between the two systems (Sec. 3.3.2, Fig. 9). That factor is a global gain calibration; it is not fitted to the baseline-noise ratio, the chi2/NDF, the timing drift, the energy threshold, or the energy resolution, so none of those reported outcomes is equal to it by construction. After amplitude scaling, baseline noise, waveform chi2, threshold, and AmBe energy-resolution results are independent measured quantities (Figs. 10, 12, 17, 19). The data-loss, LED timing-calibration, and threshold results do not depend on waveform equality across the two splitter paths. The paper's references to prior collaboration work ([5], [30], [31], [32]) supply detector characteristics, analysis software, and previous background measurements; they are ordinary method/factual citations and do not carry the load of the electronics-performance claim. The splitter-fidelity issue raised in the skeptical summary is a potential systematic/control limitation, not a case of the derivation reducing to its own inputs. No definitional equivalence, fitted-input-as-prediction, imported uniqueness, or ansatz-by-citation chain is present.

Axiom & Free-Parameter Ledger

3 free parameters · 4 axioms · 0 invented entities

No new physical entities are introduced; PDS1500 is a hardware system, not a postulated entity. The load-bearing auxiliary assumptions are the splitter fidelity, the centered-LED timing geometry, and the undocumented bit-depth simulation.

free parameters (3)
  • PDS1500-to-CAEN amplitude normalization factor = 0.04858
    Fitted from the peak-height ratio distribution (Fig. 9) using the same events as the baseline-noise and waveform comparisons; the 'one-third baseline noise' number depends on this calibration.
  • Time-calibration charge cut = 6000 ADC·ns
    Chosen by hand in Section 3.3.4 to exclude dark noise from the LED timing analysis; affects the timing-drift result.
  • Baseline fluctuation level in energy-resolution simulation = 0.5 ADC bin
    Used in Figure 19(b) to model baseline noise when concluding that bit depths above 9 do not improve energy resolution; no method for this choice is given.
axioms (4)
  • domain assumption PMT signal splitter delivers identical waveforms to both readout systems
    Section 3.1/Fig. 7: all comparative claims assume the split outputs match the input; no standalone splitter characterization is provided.
  • domain assumption LED source sits at the detector center so photon time-of-flight is equal for all PMTs
    Eq. (3) in Section 3.3.4 cancels time-of-flight only under this geometric assumption.
  • standard math Rise-time differences follow a Gaussian centered at zero and runs are statistically independent
    Used to propagate uncertainties in the time-calibration equations (4)-(6).
  • ad hoc to paper The undocumented simulation in Figure 19(b) correctly models detector energy resolution vs bit depth
    Section 3.3.6: the conclusion that >9 bits does not improve resolution relies on a simulation whose light yield, noise model, and parameters are not described.

pith-pipeline@v1.3.0-alltime-deepseek · 13662 in / 13344 out tokens · 135500 ms · 2026-08-01T13:31:58.674538+00:00 · methodology

0 comments
read the original abstract

The Jinping Neutrino Experiment (JNE), a next-generation neutrino observatory under construction at the China Jinping Underground Laboratory II (CJPL-II), requires high-precision waveform-based event reconstruction, imposing stringent demands on its readout electronics. To meet these requirements, we have developed a high-performance readout system featuring 1 GSa/s real-time sampling, 14-bit physical resolution with an effective number of bits (ENOB) of 10.6, a total data throughput of 64 Gbps, and a deterministic zero-delay clock distribution architecture. The new single-crate 64-channel system (PDS1500) was validated through bench tests and deployment on the upgraded JNE-1ton prototype detector. Its performance was further evaluated against a commercial reference system. The results demonstrate that all key metrics meet the JNE experimental requirements: zero data loss within a 1000 ns acquisition window, baseline noise reduced to one-third of the reference level, timing drift limited to 0.3 ns across power cycles, and an energy threshold as low as 0.1 MeV, enabling the detection of low-energy solar neutrinos. While the 14-bit physical resolution provides significantly higher waveform fidelity, the overall energy resolution in this test remains dominated by the intrinsic limitations of the JNE-1ton detector, as expected. Furthermore, the modular architecture provides the throughput and scalability required to support the full-scale 3000-channel JNE detector. These results collectively demonstrate that the newly developed electronics system fully satisfies the technical requirements of the future JNE experiment.

Figures

Figures reproduced from arXiv: 2607.19066 by Changxu Wei, Haoyang Fu, Haoyan Yang, Haozhe Sun, Jianmin Li, Juntao Liu, Shaomin Chen, Tao Xue, Yapeng Wang, Yinong Liu, Yuzi Yang, Zhe Wang, Zhiyi Liu.

Figure 1
Figure 1. Figure 1: The locations of JNE and JNE-1ton in Jinping and the schematic diagram of their detector. To meet the requirements of JNE, a new generation of electronic systems has been developed. The newly developed electronic single-chassis integrates a 64-channel high-speed and high-precision waveform digitization and high￾bandwidth data readout system, consisting of 8 waveform digitization boards, 1 clock and trigger… view at source ↗
Figure 2
Figure 2. Figure 2: Schematic of the data acquisition system. data buffering, digital pulse shaping, online triggering, and high speed data transmission. Additionally, a Zynq XC7Z020 SoC [25] handles board-level control, status monitoring, and remote firmware updates. Each board integrates two ADAM103 ADC mezzanine cards, providing 8 channels of 14-bit sampling at 1 GSa/s. An onboard LMK04832 [26] jitter cleaner synchronizes … view at source ↗
Figure 3
Figure 3. Figure 3: Internal boards [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: RDX051 PCIe acquisition board. • The data from each channel is evaluated against a preset threshold. The number of channels exceeding this threshold is counted and reported to the TTC308 board. The TTC308 board aggregates these over-threshold counts from all eight waveform digitization boards to determine a system-wide total. If this total exceeds a specified limit, a global trigger is simultaneously issue… view at source ↗
Figure 5
Figure 5. Figure 5: The workflow of the 60 channels electronics system. (PLL)the phases of all derived clocks remain strictly aligned with the incoming 50 MHz reference. This architecture minimizes phase skew and guarantees deterministic latency across the entire crate. This deterministic clock architecture fundamentally resolves the inter-board synchronization ambiguities com￾monly encountered in commercial legacy systems. F… view at source ↗
Figure 6
Figure 6. Figure 6: The clock distribution architecture of the 60-channel electronics system. of data collection tasks, measuring the background concentrations of natural radioactive nuclides such as 238U, 232Th, and 40K in the laboratory environment [5], as well as the precise value of the underground muon flux: (3.56 ± 0.16stat ± 0.10syst) × 10−10 cm−2 ⋅ 𝑠 −1 [31]. Beginning from 2023, we carried out a critical upgrade for … view at source ↗
Figure 7
Figure 7. Figure 7: The structure of upgraded one-ton prototype detector and the connection method with the CAEN V1751 system and PDS1500 system (the new self-developed electronics). The upgraded prototype still used the CAEN V1751 system for continuous data acquisition during the early stage of electronic testing: the FADC board V1751 was increased from 4 cards (32 channels) to 8 cards (64 channels); the Haoyan Yang and othe… view at source ↗
Figure 8
Figure 8. Figure 8: The waveforms of the same signal acquired on the CAEN V1751 and PDS1500 systems, the discrepancy in Y-axis is caused by the difference in their physical resolutions. To quantitatively compare the data in different systems, based on the statistical analysis of the distribution of peak height ratios (where peak height is defined as the difference between the signal minimum value and the baseline) of the two … view at source ↗
Figure 9
Figure 9. Figure 9: The distribution of peak height ratio values for each event in the CAEN V1751 and PDS1500 systems for a single channel, as well as the mean values of ratio and their standard deviations corresponding to all 53 channels. 0 20 40 60 Channel 0 0.5 1 1.5 Baseline noise [CAEN ADC] CAEN V1751 PDS1500 [PITH_FULL_IMAGE:figures/full_fig_p009_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Baseline noise of CAEN V1751 and PDS1500 systems of different channels. The noise level of the PDS1500 system is only one third that of the CAEN V1751 system. 3.3.3. Waveform quality When performing waveform analysis and comparison, waveform alignment is essential [PITH_FULL_IMAGE:figures/full_fig_p009_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: Example of PMT waveform alignment between CAEN V1751 and PDS1500 systems, as well as their differences. 0 1 2 3 4 /NDF 2 χ 0 5 10 15 3 ×10 Entries (a) Single channel 0 20 40 60 Channel 0 1 2/NDF 2 χ (b) 53 channels [PITH_FULL_IMAGE:figures/full_fig_p010_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: The distribution of 𝜒 2/NDF for the 10-th channel, as well as the peak positions of 𝜒 2/NDF distributions for different channels, with the error expressed in terms of the peak half-width. 3.3.4. Time drift magnitude In the detector, the PMT, signal cables, and electronic circuits will introduce inherent time offsets among channels; if this offset undergoes uncontrollable drift over time, it will significa… view at source ↗
Figure 13
Figure 13. Figure 13: Schematic diagram of the detector time calibration (left), and the signal waveforms from the 53 live PMTs collected by the PDS1500 electronics system (right). The baseline has been optimized for demonstration purposes. To comprehensively assess the long-term stability of the electronic system, we carried out 5 power-off restart operations and obtained 5 runs (Run1∼5) of independent and valid operational d… view at source ↗
Figure 14
Figure 14. Figure 14: 0 10000 20000 30000 Charge [ADC × ns] 1 10 2 10 3 10 4 10 5 10 Entries (a) Charge integration distribution / ndf 2 χ 230.5 / 108 Constant 1097 ± 6.8 Mean 3.075 ± 0.019 Sigma 3.67 ± 0.01 −40 −20 0 20 40 Rise time difference [ns] 0 0.5 1 3 ×10 Entries / ndf 2 χ 230.5 / 108 Constant 1097 ± 6.8 Mean 3.075 ± 0.019 Sigma 3.67 ± 0.01 (b) Rise time difference [PITH_FULL_IMAGE:figures/full_fig_p011_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: The time calibration result of Run1∼5 (left), and the difference in time calibration results for each channel among 5 Runs (right). 0 20 40 60 Channel −5 0 5 10 15 20 Time offset difference [ns] Run 49758 - Run 49757 Run 49759 - Run 49758 [PITH_FULL_IMAGE:figures/full_fig_p013_15.png] view at source ↗
Figure 16
Figure 16. Figure 16: The difference of time calibration result for CAEN V1751 system. There is a 16 ns clock skew between run 49758 and run 49759. energy threshold achieved by the PDS1500 system by lowering the multichannel trigger threshold (Trmulti=10): its detected spectrum only begins to drop significantly below about 0.1 MeV, whereas for other spectra with the trigger (Trmulti=45) only start to appear above 0.5 MeV. The … view at source ↗
Figure 17
Figure 17. Figure 17: The reconstructed energy spectra obtained by analyzing different datasets with the same code [5] and the upgrade detector setup itself, have their 208Tl (2.6 MeV) peaks aligned cross all spectra. Among them, spectra with Trmulti=45 are normalized spectra. For ease of comparison, the normalization method for spectrum with Trmulti=10 is to keep the area within the [2.0, 3.0] MeV range consistent with that o… view at source ↗
Figure 18
Figure 18. Figure 18: The time difference (Δ𝑡) distributions of the promptdelay signals obtained using the similar packing code [5] are shown. After fitting with an exponential plus constant function: Const × 𝑒 − Δ𝑡 𝜏 + B, the neutron capture lifetime 𝜏 is obtained, the background B is fixed as the mean count within the time window [1000, 2000] 𝜇s. 1 1.5 2 2.5 3 E [MeV] 0 100 200 300 CAEN A.U 0 10 20 30 40 50 PDS1500 A.U PDS15… view at source ↗
Figure 19
Figure 19. Figure 19: (a)The neutron capture energy spectra measured by the PDS1500 and CAEN V1751 systems, which are fitted using the crystal ball function. (b)The energy resolution of the detector decreases with increasing ADC bit number of the electronics. When the bit number reaches 9 bits, the resolution approaches the limit at the intrinsic energy resolution 9.0%. Meanwhile, the influence of baseline noise on the resolut… view at source ↗
Figure 20
Figure 20. Figure 20: The workflow of the 3000 channels electronics system. 4.2. Clock distribution structure The precision of neutrino event reconstruction relies heavily on a unified and stable timing reference across all 3000 channels. As depicted in [PITH_FULL_IMAGE:figures/full_fig_p016_20.png] view at source ↗
Figure 21
Figure 21. Figure 21: The Clock distribution structure of the 3000 channels electronics system. 5. Conclusion To meet the waveform acquisition and high-speed data transmission requirements of the future JNE experiment, which demands readout from approximately 3,000 PMTs, we have independently developed the PDS1500 electronics systema single-crate 64-channel platformand validated it on the upgraded JNE-1ton prototype detector a… view at source ↗

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