Implementation of mean-timing and subsequent logic functions on an FPGA

C. Schill; F. Herrmann; F. Klein; G. Ahluwalia; H. Fischer; J. Barth; J. Bieling; J. Pretz; S. Schopferer

REVIEW

Implementation of mean-timing and subsequent logic functions on an FPGA

Not yet reviewed by Pith; the record is open.

Re-run · record.json Download PDF Read on arXiv ↗

This paper has not been read by Pith yet. Machine review is queued; the pith claim, tier, and objections will appear here once it completes.

SPECIMEN: schema-true, not a live event

T0 review · schema-true

One-sentence machine reading of the paper's core claim.

pith:XXXXXXXX · record.json · timestamp

arxiv 1109.4735 v2 pith:RGF4FFZ3 submitted 2011-09-22 physics.ins-det

Implementation of mean-timing and subsequent logic functions on an FPGA

J. Bieling , G. Ahluwalia , J. Barth , F. Klein , J. Pretz , H. Fischer , F. Herrmann , C. Schill

show 1 more author

S. Schopferer

This is my paper

classification physics.ins-det

keywords logicclockcoincidencefpgaimplementationmean-timingallowsapproximately

verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

0 comments

Share X Bluesky LinkedIn Reddit HN

read the original abstract

This article describes the implementation of a mean-timer and coincidence logic on a Virtex-5 FPGA for trigger purposes in a particle physics experiment. The novel feature is that the mean-timing and the coincidence logic are not synchronized with a clock which allows for a higher resolution of approximately 400 ps, not limited by a clock frequency.

Implementation of mean-timing and subsequent logic functions on an FPGA

discussion (0)