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Flush+Flush: A Fast and Stealthy Cache Attack

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arxiv 1511.04594 v3 pith:ILXRIS7U submitted 2015-11-14 cs.CR

classification cs.CR
keywords flushcacheattackattacksdetectionhitsmisseschannel
verification ladder T0 review T1 audit T2 compute T3 formal
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Research on cache attacks has shown that CPU caches leak significant information. Proposed detection mechanisms assume that all cache attacks cause more cache hits and cache misses than benign applications and use hardware performance counters for detection. In this article, we show that this assumption does not hold by developing a novel attack technique: the Flush+Flush attack. The Flush+Flush attack only relies on the execution time of the flush instruction, which depends on whether data is cached or not. Flush+Flush does not make any memory accesses, contrary to any other cache attack. Thus, it causes no cache misses at all and the number of cache hits is reduced to a minimum due to the constant cache flushes. Therefore, Flush+Flush attacks are stealthy, i.e., the spy process cannot be detected based on cache hits and misses, or state-of-the-art detection mechanisms. The Flush+Flush attack runs in a higher frequency and thus is faster than any existing cache attack. With 496 KB/s in a cross-core covert channel it is 6.7 times faster than any previously published cache covert channel.

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Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Modern Hardware Security: A Review of Attacks and Countermeasures

    cs.CR 2025-01 conditional

    This is a literature review of hardware security attacks and countermeasures, with no new attacks, mitigations, measurements, or proofs.

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