Pith. sign in

REVIEW

Gate-tunable, normally-on to normally-off memristance transition in patterned LaAlO3/SrTiO3 interfaces

Not yet reviewed by Pith; the record is open.

This paper has not been read by Pith yet. Machine review is queued; the pith claim, tier, and objections will appear here once it completes.

SPECIMEN: schema-true, not a live event

T0 review · schema-true

One-sentence machine reading of the paper's core claim.

pith:XXXXXXXX · record.json · timestamp

arxiv 1610.05146 v2 pith:6XDKCN5D submitted 2016-10-17 cond-mat.mes-hall

classification cond-mat.mes-hall
keywords gatememristanceannealingmemristivevoltagesdevicegate-tunableinterfaces
verification ladder T0 review T1 audit T2 compute T3 formal
0 comments
read the original abstract

We report gate-tunable memristive switching in patterned LaAlO3/SrTiO3 interfaces at cryogenic temperatures. The application of voltages in the order of a few volts to the back gate of the device allows controlling and switching-on and -off the inherent memory functionality (memristance). For large and small gate voltages a simple non-linear resistance characteristic is observed while a pinched hysteresis loop and memristive switching occurs in an intermediate voltage range. The memristance is further controlled by the density of oxygen vacancies, which is tuned by annealing the sample at 300 {\deg}C in nitrogen atmosphere. Depending on the annealing time the memristance at zero gate voltage can be switched on and off leading to normally-on and normally-off memristors. The presented device offers reversible and irreversible control of memristive characteristics by gate voltages and annealing, respectively, which may allow to compensate fabrication variabilities of memristors that complicate the realization of large memristor-based neural networks.

Discussion (0). Sign in to comment.

Pith tools