Analog CMOS-based Resistive Processing Unit for Deep Neural Network Training

Hyung-Min Lee; Seyoung Kim; Tayfun Gokmen; Wilfried E. Haensch

arxiv: 1706.06620 · v1 · pith:PRXYQ7G6new · submitted 2017-06-20 · 💻 cs.ET · cs.LG

Analog CMOS-based Resistive Processing Unit for Deep Neural Network Training

Seyoung Kim , Tayfun Gokmen , Hyung-Min Lee , Wilfried E. Haensch This is my paper

classification 💻 cs.ET cs.LG

keywords trainingaccelerationanalogcmoscmos-baseddeepnetworkneural

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Recently we have shown that an architecture based on resistive processing unit (RPU) devices has potential to achieve significant acceleration in deep neural network (DNN) training compared to today's software-based DNN implementations running on CPU/GPU. However, currently available device candidates based on non-volatile memory technologies do not satisfy all the requirements to realize the RPU concept. Here, we propose an analog CMOS-based RPU design (CMOS RPU) which can store and process data locally and can be operated in a massively parallel manner. We analyze various properties of the CMOS RPU to evaluate the functionality and feasibility for acceleration of DNN training.

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On-chip learning in a conventional silicon MOSFET based Analog Hardware Neural Network
cs.NE 2019-07 unverdicted novelty 5.0

SPICE simulations demonstrate on-chip learning in a fully connected neural network using conventional MOSFETs as synapses, achieving high accuracy on the Iris dataset with performance comparable to NVM-based systems.