RECORD
Weak Memory Models: Balancing Definitional Simplicity and Implementation Flexibility
Programming Languages · Submitted 19 Jul 2017
abstract compiled · 2026-09-23 · no language-model review
The authors' main claim We propose two new weak memory models: WMM and WMM-S, which balance definitional simplicity and implementation flexibility differently.
The compiled record
The paper's own sentences, arranged. Each label is drawn from a closed vocabulary; the number beside it is the probability the classifier gave that label. Numbers in the tables are the authors', checked by code. No sentence in this record was written by a model.
Open the compiled record
The abstract, sentence by sentence
The memory model for RISC-V, a newly developed open source ISA, has not been finalized yet and thus, offers an opportunity to evaluate existing memory models. We believe RISC-V should not adopt the memory models of POWER or ARM, because their axiomatic and operational definitions are too complicated. We propose two new weak memory models: WMM and WMM-S, which balance definitional simplicity and implementation flexibility differently. Both allow all instruction reorderings except overtaking of loads by a store. We show that this restriction has little impact on performance and it considerably simplifies operational definitions. It also rules out the out-of-thin-air problem that plagues many definitions. WMM is simple (it is similar to the Alpha memory model), but it disallows behaviors arising due to shared store buffers and shared write-through caches (which are seen in POWER processors). WMM-S, on the other hand, is more complex and allows these behaviors. We give the operational definitions of both models using Instantaneous Instruction Execution (I2E), which has been used in the definitions of SC and TSO. We also show how both models can be implemented using conventional cache-coherent memory systems and out-of-order processors, and encompasses the behaviors of most known optimizations.
background contribution method result interpretation main claim
| # | sentence | role | the authors' own work | states the main conclusion | strength |
|---|---|---|---|---|---|
| s0 | The memory model for RISC-V, a newly developed open source ISA, has not been finalized yet and thus, offers an opportunity to evaluate existing memory models. | background 0.95 | 0.08 | 0.03 | asserted 0.98 |
| s1 | We believe RISC-V should not adopt the memory models of POWER or ARM, because their axiomatic and operational definitions are too complicated. | background 0.72 | 0.18 | 0.15 | asserted 0.44 |
| s2 | We propose two new weak memory models: WMM and WMM-S, which balance definitional simplicity and implementation flexibility differently. | contribution 1.00 | 0.88 | 0.50 | asserted 1.00 |
| s3 | Both allow all instruction reorderings except overtaking of loads by a store. | contribution 0.83 | 0.47 | 0.14 | asserted 1.00 |
| s4 | We show that this restriction has little impact on performance and it considerably simplifies operational definitions. | result 0.90 | 0.89 | 0.20 | asserted 1.00 |
| s5 | It also rules out the out-of-thin-air problem that plagues many definitions. | result 0.81 | 0.72 | 0.11 | asserted 1.00 |
| s6 | WMM is simple (it is similar to the Alpha memory model), but it disallows behaviors arising due to shared store buffers and shared write-through caches (which are seen in POWER processors). | contribution 0.60 | 0.45 | 0.09 | asserted 1.00 |
| s7 | WMM-S, on the other hand, is more complex and allows these behaviors. | contribution 0.93 | 0.52 | 0.08 | asserted 1.00 |
| s8 | We give the operational definitions of both models using Instantaneous Instruction Execution (I2E), which has been used in the definitions of SC and TSO. | method 0.87 | 0.88 | 0.05 | asserted 1.00 |
| s9 | We also show how both models can be implemented using conventional cache-coherent memory systems and out-of-order processors, and encompasses the behaviors of most known optimizations. | contribution 0.79 | 0.91 | 0.21 | asserted 0.99 |
What was examined, and what was not
- arXiv listing abstract v2
- full text
- figures and tables
- references and citing sentences
- relations to other papers
- P abstract
- S sections
- T body sentences
- C citations
- R cross-paper relations
The paper
Original abstract
The memory model for RISC-V, a newly developed open source ISA, has not been finalized yet and thus, offers an opportunity to evaluate existing memory models. We believe RISC-V should not adopt the memory models of POWER or ARM, because their axiomatic and operational definitions are too complicated. We propose two new weak memory models: WMM and WMM-S, which balance definitional simplicity and implementation flexibility differently. Both allow all instruction reorderings except overtaking of loads by a store. We show that this restriction has little impact on performance and it considerably simplifies operational definitions. It also rules out the out-of-thin-air problem that plagues many definitions. WMM is simple (it is similar to the Alpha memory model), but it disallows behaviors arising due to shared store buffers and shared write-through caches (which are seen in POWER processors). WMM-S, on the other hand, is more complex and allows these behaviors. We give the operational definitions of both models using Instantaneous Instruction Execution (I2E), which has been used in the definitions of SC and TSO. We also show how both models can be implemented using conventional cache-coherent memory systems and out-of-order processors, and encompasses the behaviors of most known optimizations.
Human review
Discussion
Know something about this paper? Leave a comment, or highlight any passage above to comment on it.