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A software framework for pipelined arithmetic algorithms in field programmable gate arrays
Other Computer Science · Submitted 20 Oct 2017
abstract compiled · 2026-09-23 · no language-model review
The authors' main claim We present a $\texttt{C++}$ software framework which automatically simulates and generates hardware description language code for pipelined arithmetic algorithms.
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The abstract, sentence by sentence
Pipelined algorithms implemented in field programmable gate arrays are being extensively used for hardware triggers in the modern experimental high energy physics field and the complexity of such algorithms are increases rapidly. For development of such hardware triggers, algorithms are developed in $\texttt{C++}$, ported to hardware description language for synthesizing firmware, and then ported back to $\texttt{C++}$ for simulating the firmware response down to the single bit level. We present a $\texttt{C++}$ software framework which automatically simulates and generates hardware description language code for pipelined arithmetic algorithms.
background contribution method result interpretation main claim
| # | sentence | role | the authors' own work | states the main conclusion | strength |
|---|---|---|---|---|---|
| s0 | Pipelined algorithms implemented in field programmable gate arrays are being extensively used for hardware triggers in the modern experimental high energy physics field and the complexity of such algorithms are increases rapidly. | background 1.00 | 0.06 | 0.03 | asserted 1.00 |
| s1 | For development of such hardware triggers, algorithms are developed in $\texttt{C++}$, ported to hardware description language for synthesizing firmware, and then ported back to $\texttt{C++}$ for simulating the firmware response down to the single bit level. | background 0.95 | 0.17 | 0.04 | asserted 1.00 |
| s2 | We present a $\texttt{C++}$ software framework which automatically simulates and generates hardware description language code for pipelined arithmetic algorithms. | contribution 1.00 | 0.94 | 0.65 | asserted 1.00 |
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The paper
Original abstract
Pipelined algorithms implemented in field programmable gate arrays are being extensively used for hardware triggers in the modern experimental high energy physics field and the complexity of such algorithms are increases rapidly. For development of such hardware triggers, algorithms are developed in $\texttt{C++}$, ported to hardware description language for synthesizing firmware, and then ported back to $\texttt{C++}$ for simulating the firmware response down to the single bit level. We present a $\texttt{C++}$ software framework which automatically simulates and generates hardware description language code for pipelined arithmetic algorithms.
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How the literature uses it
1 arXiv paper cite this in 2 sentences
Papers citing it · 1 sentence without a confident label
Uses its method or tool 1 paper
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By using the two dimensional track information, the geometrically possible stereo TSs are calculated where a framework that automatically generates VHDL was used for development [ref] .
Three dimensional fast tracker for central drift chamber based level 1 trigger system in the Belle II experiment · Stereo TS finder · 0.98
What it cites · 3 sentences without a confident label
Uses the method or tool of 1 paper
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The transformation equations are [equation] where $ϕ_fineSt$ is the fine phi position of a hit stereo wire (wires that have a finite phi shift at the end plates) , $ϕ_st$ is the phi position of a hit stereo wire, TDC is the wire hit time relative to the revolution of the beam, $t_0$ is the event time relative to the revolution of the beam, $LUT$ is a look up table that has the x-t curve of the CDC, $ϕ_ax$ is the phi position if a stereo wire is an axial wire (wires that are parallel to the beam) , $r$ is the radius of a stereo wire layer, $ρ$ is the curvature of a track, $ϕ_incident$ is the incident angle of a track, $z$ is the geometric hit position, $z_endplate$ is the distance from the IP to the end plate of the CDC, and $s$ is the arc length of the track in a two dimensional plane for a stereo wire layer [ref] .
Three dimensional fast tracker for central drift chamber based level 1 trigger system in the Belle II experiment · $χ^2$ minimization fitters · 0.80
Cites as background 1 paper
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The Belle II experiment [ref] aims to study the charge-conjugation and the parity violation in $B$ or $D$ meson system precisely and search for new physics at the SuperKEKB accelerator [ref] .
Belle II Technical Design Report · Implementation examples · 1.00
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