Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links
Paper Citation Record · LEDGER
The EPFL Logic Synthesis Libraries
As of 11 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 6 inbound Pith citation observations for arXiv:1805.05121.
A citation records a reference. It does not transfer a finding from one paper to another.
Coverage vector
One-hop event checks from named stored sources.
Source: scholarly_work_events, retraction_status_cache, observed 2026-08-11T06:34:44.6726+00:00
Pith citing papers itemized under the disclosed page cap.
Source: paper_references, paper_reference_links, observed 2026-08-10T16:27:04.057227Z
A source-named dated measurement, never combined with another source.
Source: pith, observed 2026-07-09T18:46:26.497290Z
Reference resolution
0 of 0 outbound references displayed
- verified exact0
- verified fuzzy0
- unresolved0
- parse uncertain0
- malformed identifier0
- metadata mismatch0
External citation measurements
No source-named external measurement is stored.
Outbound references
No outbound reference observations are available for this paper version.
Pith citing papers
Observation 601c9b33-cffe-4ff1-bf86-1d6e1df0675b · inbound
ASDF: A Compiler for Qwerty, a Basis-Oriented Quantum Programming Language cites this paper.
ASDF: A Compiler for Qwerty, a Basis-Oriented Quantum Programming Language The EPFL Logic Synthesis Libraries
Reference 52
- Resolution
- unresolved
- no resolver link, observed 2026-08-10T16:27:04.057227Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation bbf82363-c9ce-44a5-8df8-1b273d503c64 · inbound
Cut Tracing with E-Graphs for Boolean FHE Circuit Synthesis cites this paper.
Cut Tracing with E-Graphs for Boolean FHE Circuit Synthesis The EPFL Logic Synthesis Libraries
Reference 9
- Resolution
- unresolved
- no resolver link, observed 2026-08-07T00:39:34.154130Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 1694d0d3-c9b1-49d4-be20-05eebe20e94d · inbound
Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper cites this paper.
Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper The EPFL Logic Synthesis Libraries
Reference 10
- Resolution
- unresolved
- no resolver link, observed 2026-08-06T17:29:20.390547Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 8da8ea28-be64-49f1-bb2e-c156ceab31bc · inbound
Explicit Sign-Magnitude Encoders Enable Power-Efficient Multipliers cites this paper.
Explicit Sign-Magnitude Encoders Enable Power-Efficient Multipliers The EPFL Logic Synthesis Libraries
Reference 19
- Resolution
- unresolved
- no resolver link, observed 2026-08-06T14:44:51.127255Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation c8627dc8-825b-4e84-9f2b-d8af9bc0cc7a · inbound
RTLScout: Joint Agentic Code and Synthesis Optimization for Efficient Digital Circuits cites this paper.
RTLScout: Joint Agentic Code and Synthesis Optimization for Efficient Digital Circuits The EPFL Logic Synthesis Libraries
Reference 30
- Resolution
- metadata mismatch
- arxiv_id, observed 2026-07-02T11:26:54.346386Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.
Observation 7a48e455-9b0e-4855-a757-110bf73e0fd5 · inbound
Miter-Aware LUT Mapping: Aligning Structure and Solvability for Efficient Logic Equivalence Checking cites this paper.
Miter-Aware LUT Mapping: Aligning Structure and Solvability for Efficient Logic Equivalence Checking The EPFL Logic Synthesis Libraries
Reference 38
- Resolution
- verified exact
- local_arxiv, observed 2026-07-09T18:46:26.498796Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.