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Speculative Buffer Overflows: Attacks and Defenses

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arxiv 1807.03757 v1 pith:AMHWSNY7 submitted 2018-07-10 cs.CR

classification cs.CR
keywords speculativeattacksmitigationsbufferoverflowssoftwarecodehardware
verification ladder T0 review T1 audit T2 compute T3 formal
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Practical attacks that exploit speculative execution can leak confidential information via microarchitectural side channels. The recently-demonstrated Spectre attacks leverage speculative loads which circumvent access checks to read memory-resident secrets, transmitting them to an attacker using cache timing or other covert communication channels. We introduce Spectre1.1, a new Spectre-v1 variant that leverages speculative stores to create speculative buffer overflows. Much like classic buffer overflows, speculative out-of-bounds stores can modify data and code pointers. Data-value attacks can bypass some Spectre-v1 mitigations, either directly or by redirecting control flow. Control-flow attacks enable arbitrary speculative code execution, which can bypass fence instructions and all other software mitigations for previous speculative-execution attacks. It is easy to construct return-oriented-programming (ROP) gadgets that can be used to build alternative attack payloads. We also present Spectre1.2: on CPUs that do not enforce read/write protections, speculative stores can overwrite read-only data and code pointers to breach sandboxes. We highlight new risks posed by these vulnerabilities, discuss possible software mitigations, and sketch microarchitectural mechanisms that could serve as hardware defenses. We have not yet evaluated the performance impact of our proposed software and hardware mitigations. We describe the salient vulnerability features and additional hypothetical attack scenarios only to the detail necessary to guide hardware and software vendors in threat analysis and mitigations. We advise users to refer to more user-friendly vendor recommendations for mitigations against speculative buffer overflows or available patches.

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Forward citations

Cited by 4 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Analyzing and Exploiting Branch Mispredictions in Microcode

    cs.CR 2025-01 conditional novelty 8.0 of 10

    µSpectre is a new class of transient execution attacks that exploits statically-not-taken microcode branches in Intel CPUs, reclassifies known attacks, and adds a microcode defense.

  2. Oreo: Protecting ASLR Against Microarchitectural Attacks (Extended Version)

    cs.CR 2024-12 conditional novelty 7.0 of 10

    Oreo translates virtual addresses into a masked address space before they reach caches, TLBs, and branch predictors, preventing microarchitectural side channels from revealing the ASLR secret offset.

  3. dfence: Fine-Grained Speculation Barriers for Efficient and Effective Hardware-Software Protection in the Spectre Era (Extended Version)

    cs.CR 2026-08 conditional novelty 6.0 of 10

    A new dfence instruction plus a formally-analyzed type system blocks Spectre-PHT and Spectre-STL leakage on the Proteus RISC-V core with negligible performance cost.

  4. Modern Hardware Security: A Review of Attacks and Countermeasures

    cs.CR 2025-01 conditional

    This is a literature review of hardware security attacks and countermeasures, with no new attacks, mitigations, measurements, or proofs.

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