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An Analysis Framework for Hardware and Software Implementations with Applications from Cryptography
Distributed, Parallel, and Cluster Computing · Submitted 30 Mar 2019
abstract compiled · 2026-09-23 · no language-model review
The authors' main claim This paper confirms that a unified statistical framework can successfully classify algorithms based on a combination of the heterogeneous characteristics of their hardware and software implementations.
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The abstract, sentence by sentence
With the richness of present-day hardware architectures, tightening the synergy between hardware and software has attracted a great attention. The interest in unified approaches paved the way for newborn frameworks that target hardware and software co-design. This paper confirms that a unified statistical framework can successfully classify algorithms based on a combination of the heterogeneous characteristics of their hardware and software implementations. The proposed framework produces customizable indicators for any hybridization of processing systems and can be contextualized for any area of application. The framework is used to develop the Lightness Indicator System (LIS) as a case-study that targets a set of cryptographic algorithms that are known in the literature to be tiny and light. The LIS targets state-of-the-art multi-core processors and high-end Field Programmable Gate Arrays (FPGAs). The presented work includes a generic benchmark model that aids the clear presentation of the framework and extensive performance analysis and evaluation.
background contribution method result interpretation main claim
| # | sentence | role | the authors' own work | states the main conclusion | strength |
|---|---|---|---|---|---|
| s0 | With the richness of present-day hardware architectures, tightening the synergy between hardware and software has attracted a great attention. | background 1.00 | 0.05 | 0.02 | asserted 1.00 |
| s1 | The interest in unified approaches paved the way for newborn frameworks that target hardware and software co-design. | background 1.00 | 0.06 | 0.03 | asserted 1.00 |
| s2 | This paper confirms that a unified statistical framework can successfully classify algorithms based on a combination of the heterogeneous characteristics of their hardware and software implementations. | result 0.81 | 0.86 | 0.89 | asserted 0.99 |
| s3 | The proposed framework produces customizable indicators for any hybridization of processing systems and can be contextualized for any area of application. | contribution 0.87 | 0.75 | 0.11 | asserted 0.98 |
| s4 | The framework is used to develop the Lightness Indicator System (LIS) as a case-study that targets a set of cryptographic algorithms that are known in the literature to be tiny and light. | contribution 0.78 | 0.89 | 0.05 | asserted 0.99 |
| s5 | The LIS targets state-of-the-art multi-core processors and high-end Field Programmable Gate Arrays (FPGAs). | contribution 0.67 | 0.51 | 0.03 | asserted 1.00 |
| s6 | The presented work includes a generic benchmark model that aids the clear presentation of the framework and extensive performance analysis and evaluation. | method 0.66 | 0.90 | 0.04 | asserted 1.00 |
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The paper
Original abstract
With the richness of present-day hardware architectures, tightening the synergy between hardware and software has attracted a great attention. The interest in unified approaches paved the way for newborn frameworks that target hardware and software co-design. This paper confirms that a unified statistical framework can successfully classify algorithms based on a combination of the heterogeneous characteristics of their hardware and software implementations. The proposed framework produces customizable indicators for any hybridization of processing systems and can be contextualized for any area of application. The framework is used to develop the Lightness Indicator System (LIS) as a case-study that targets a set of cryptographic algorithms that are known in the literature to be tiny and light. The LIS targets state-of-the-art multi-core processors and high-end Field Programmable Gate Arrays (FPGAs). The presented work includes a generic benchmark model that aids the clear presentation of the framework and extensive performance analysis and evaluation.
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