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arxiv: 1907.02732 · v1 · pith:WHOJJTJ3new · submitted 2019-07-05 · ⚛️ physics.ins-det

Design and testing of a bunch-by-bunch beam position transverse feedback processor

Linsong Zhan , Lei Zhao , Jinxin Liu , Shubin Liu , Qi An This is my paper

Pith reviewed 2026-05-25 02:10 UTC · model grok-4.3

classification ⚛️ physics.ins-det
keywords bunch-by-bunch feedbacktransverse feedbackclock synchronizationPLLdelay linesbeam position processormulti-bunch instabilitysynchrotron storage ring
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The pith

A PLL and delay line synchronization method enables precise bunch-by-bunch transverse feedback with over 9-bit ADC resolution and 40 dB closed-loop attenuation.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents the design of a processor for a bunch-by-bunch transverse feedback system at the SSRF storage ring, where multi-bunch instabilities currently limit stored beam current. The central innovation is a clock synchronization and precise delay adjustment technique built around phase-locked loops combined with delay lines, which addresses the need for accurate timing at the 499.654 MHz bunch rate. Laboratory measurements confirm that the analog-to-digital conversion maintains an effective number of bits above 9 across 100 kHz to 700 MHz, while the closed-loop system delivers more than 40 dB attenuation at critical frequencies. Initial tests with actual beam signals produce results matching these specifications.

Core claim

The authors demonstrate that a novel synchronization architecture using PLLs and delay lines achieves the timing precision required for effective bunch-by-bunch transverse feedback. This yields an ADC effective number of bits better than 9 bits from 100 kHz to 700 MHz and closed-loop attenuation exceeding 40 dB at key frequencies, with beam commissioning results at SSRF remaining consistent with laboratory expectations.

What carries the argument

The PLLs and delay lines clock synchronization and precise delay adjustment method that aligns sampling with the 499.654 MHz bunch rate.

If this is right

  • The processor can damp transverse multi-bunch instabilities and thereby raise the maximum stored current at SSRF.
  • Precise per-bunch timing alignment at 499.654 MHz enables independent correction of each of the 720 bunches.
  • The wideband ADC performance supports feedback across the full range of relevant beam oscillation frequencies.
  • Consistent beam-test results indicate the system can be commissioned without major retuning of the synchronization chain.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same PLL-plus-delay-line approach could be adapted to other storage rings that require bunch-by-bunch feedback at comparable or higher harmonic numbers.
  • Embedding the synchronization block inside a larger digital signal processor might allow real-time adjustment of delay values in response to measured beam conditions.
  • If timing jitter sources are characterized more fully, the method could serve as a template for feedback processors at future higher-current light sources.

Load-bearing premise

Performance measured with external laboratory test signals will hold when the processor operates inside the full closed-loop system driven by real beam-induced position signals at the operating bunch rate and with all sources of timing jitter present.

What would settle it

A direct measurement of closed-loop attenuation falling below 40 dB when the processor is driven by actual beam position signals at 499.654 MHz bunch rate would falsify the claim that the reported laboratory performance transfers to operational conditions.

Figures

Figures reproduced from arXiv: 1907.02732 by Jinxin Liu, Lei Zhao, Linsong Zhan, Qi An, Shubin Liu.

Figure 1
Figure 1. Figure 1: Architecture of the overall beam transverse feedback system. [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Structure of the beam position transverse feedback processor. [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Block diagram of the ADC front-end circuit. [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: S11 parameter simulation results. Fig.5. Amplitude response simulation results [PITH_FULL_IMAGE:figures/full_fig_p003_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Fig.5. Amplitude response simulation results. [PITH_FULL_IMAGE:figures/full_fig_p003_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Phase response simulation results. 2.2 Design of clock generation and fine delay adjustment circuits The feedback system relies on a strict timing [8] (a precision better than 20 ps is preferred for SSRF). First, the sampling clock phase of an ADC needs to be finely adjusted (with a step size of 10 ps) to make the samples at the bunch waveform nearby its peak, in order to improve the Signal to Noise Ratio … view at source ↗
Figure 7
Figure 7. Figure 7: Block diagram of the clock generation and delay adjustment circuits. [PITH_FULL_IMAGE:figures/full_fig_p004_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Timing diagram of key clock signals after delay adjustment. [PITH_FULL_IMAGE:figures/full_fig_p004_8.png] view at source ↗
Figure 10
Figure 10. Figure 10: Timing diagram of the data transfer between the FPGA and DAC. [PITH_FULL_IMAGE:figures/full_fig_p005_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: Block diagram of the digital signal processing algorithm. [PITH_FULL_IMAGE:figures/full_fig_p005_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Structure of the FIR filter. 2.5 Data Buffering and Transfer The beam position transverse feedback processor is based on the 6U PXI standard. As shown in [PITH_FULL_IMAGE:figures/full_fig_p006_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: Block diagram of the data transfer. III. TEST RESULTS To evaluate the performance of the processor, we conducted a series of tests both in the laboratory and with the accelerator beam [PITH_FULL_IMAGE:figures/full_fig_p006_13.png] view at source ↗
Figure 14
Figure 14. Figure 14: System under test. 3.1.1 ADC Performance Test First, we conducted tests on the ADC, which is one of the key parts of the feedback processor. Dynamic analysis of the ADC was conducted based on the IEEE Std.1241-2010 [21] to assess the circuit performance. We used the Fast Fourier Transformation and spectral averaging method (4 data sections, each section containing 16384 sampling points). Further we change… view at source ↗
Figure 15
Figure 15. Figure 15: The ENOB dependence on the input frequency. Fig. 16. The SINAD dependence on the input frequency. [PITH_FULL_IMAGE:figures/full_fig_p007_15.png] view at source ↗
Figure 17
Figure 17. Figure 17: Non-linearity test results of the DAC circuits, (a) DNL and (b) INL. [PITH_FULL_IMAGE:figures/full_fig_p007_17.png] view at source ↗
Figure 18
Figure 18. Figure 18: DelayLine1 adjustment test results, (a) clock signal waveforms and (b) delay time test results. [PITH_FULL_IMAGE:figures/full_fig_p008_18.png] view at source ↗
Figure 19
Figure 19. Figure 19: DelayLine2 adjustment test results, (a) clock signal waveforms and (b) delay time test results. [PITH_FULL_IMAGE:figures/full_fig_p008_19.png] view at source ↗
Figure 20
Figure 20. Figure 20: The spectrum of frequency plots, (a) phase vs frequency plot and (b) amplitude vs frequency plot. [PITH_FULL_IMAGE:figures/full_fig_p008_20.png] view at source ↗
Figure 22
Figure 22. Figure 22: The frequency spectrum of the beam position, (a) before and (b) after the feedback function turned on. [PITH_FULL_IMAGE:figures/full_fig_p009_22.png] view at source ↗
read the original abstract

Shanghai Synchrotron Radiation Facility (SSRF) is a 3.5 GeV storage ring with a bunch rate of 499.654 MHz, harmonic number of 720, and circumference of 432 meters. SSRF injection works at 3.5 GeV, where the multi-bunch instabilities limit the maximum stored current. In order to suppress multi-bunch instabilities caused by transverse impedance, a bunch-by-bunch transverse feedback system is indispensable for SSRF. The key component of that system is the bunch-by-bunch transverse feedback electronics. An important task in the electronics is precise time synchronization. In this paper, a novel clock synchronization and precise delay adjustment method based on the PLLs and delay lines are proposed. Test results indicate that the ENOB (Effective Number Of Bits) of the analog-to-digital conversion circuit is better than 9 bits in the input signal frequency range from 100 kHz to 700 MHz, and the closed loop attenuation at the critical frequency points is better than 40 dB. The initial commissioning tests with the beam in SSRF are also conducted, and the results are consistent with the expectations.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The manuscript describes the design of a bunch-by-bunch transverse feedback processor for the SSRF 3.5 GeV storage ring (bunch rate 499.654 MHz). It proposes a novel clock synchronization and delay adjustment method using PLLs and delay lines, reports laboratory measurements of the ADC circuit with ENOB better than 9 bits from 100 kHz to 700 MHz and closed-loop attenuation better than 40 dB at critical frequencies, and states that initial beam commissioning results are consistent with expectations.

Significance. If the reported laboratory performance translates to the operational environment with real beam-induced signals, the processor would provide a practical tool for suppressing multi-bunch transverse instabilities, enabling higher stored currents at SSRF and similar light sources. The PLL/delay-line synchronization approach, if robust, addresses a key engineering challenge in high-frequency bunch-by-bunch feedback.

major comments (2)
  1. [Beam commissioning section] Beam commissioning section: the statement that results are 'consistent with the expectations' supplies no quantitative metrics (e.g., measured attenuation at the same critical frequencies, position resolution, or instability growth rates) under actual beam conditions at 499.654 MHz bunch rate. This is load-bearing for the central claim because the ENOB and 40 dB attenuation figures were obtained with external synthesized signals.
  2. [Test results section] Test results section: the ENOB and closed-loop attenuation data are acquired with laboratory test signals; no side-by-side comparison or error budget is provided to show that PLL synchronization and ADC performance remain unchanged when the processor is driven by real beam pickup signals that include all sources of timing jitter present in the storage ring.
minor comments (1)
  1. The measurement protocols, uncertainty budgets, and exact definition of 'critical frequency points' for the 40 dB attenuation claim should be stated explicitly so that the laboratory results can be reproduced and compared with future beam data.

Simulated Author's Rebuttal

2 responses · 2 unresolved

We thank the referee for the careful and constructive review. We address each major comment below, indicating where revisions will be made to the manuscript.

read point-by-point responses

  1. Referee: [Beam commissioning section] Beam commissioning section: the statement that results are 'consistent with the expectations' supplies no quantitative metrics (e.g., measured attenuation at the same critical frequencies, position resolution, or instability growth rates) under actual beam conditions at 499.654 MHz bunch rate. This is load-bearing for the central claim because the ENOB and 40 dB attenuation figures were obtained with external synthesized signals.

    Authors: We agree that the beam commissioning section would be strengthened by quantitative metrics. The initial tests confirmed that the processor could be synchronized to the 499.654 MHz bunch rate and that feedback could be applied without introducing new instabilities, which was consistent with laboratory expectations. However, detailed quantitative data (such as attenuation at specific frequencies or growth-rate measurements) were not recorded during these preliminary beam tests. In the revised manuscript we will expand the section with all available quantitative observations from commissioning and will explicitly note the qualitative nature of the beam results. revision: partial

  2. Referee: [Test results section] Test results section: the ENOB and closed-loop attenuation data are acquired with laboratory test signals; no side-by-side comparison or error budget is provided to show that PLL synchronization and ADC performance remain unchanged when the processor is driven by real beam pickup signals that include all sources of timing jitter present in the storage ring.

    Authors: The laboratory measurements were performed with synthesized signals locked to the exact bunch frequency to emulate the timing environment. The PLL-and-delay-line architecture is specifically intended to maintain synchronization against ring timing variations. We will add a short discussion in the revised manuscript explaining the design features that limit sensitivity to additional beam-induced jitter and why the reported ENOB and attenuation figures are expected to remain representative. revision: yes

standing simulated objections not resolved
  • Quantitative beam commissioning metrics (attenuation, position resolution, growth rates) at the critical frequencies under operational conditions
  • Explicit side-by-side comparison or error budget between laboratory and real beam-pickup signals

Circularity Check

0 steps flagged

No circularity; empirical hardware measurements with no derivation chain

full rationale

The paper describes a hardware design for clock synchronization using PLLs and delay lines, then reports direct laboratory measurements of ENOB (>9 bits) and closed-loop attenuation (>40 dB) using external test signals, plus qualitative initial beam commissioning. No equations, predictions, fitted parameters, or first-principles derivations are presented that could reduce to their own inputs. No self-citations are invoked as load-bearing uniqueness theorems. The central claims rest on bench data rather than any tautological loop, consistent with the reader's score of 1.0. This is the expected outcome for a pure instrumentation/testing manuscript.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

The work uses standard electronics components and measurement practices; no free parameters, domain axioms, or invented entities are introduced or required by the abstract.

pith-pipeline@v0.9.0 · 5741 in / 1152 out tokens · 34158 ms · 2026-05-25T02:10:51.279942+00:00 · methodology

discussion (0)

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Reference graph

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