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The performance wall of parallelized sequential computing: the dark performance and the roofline of performance gain

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arxiv 1908.02280 v1 pith:ACI4N2MM submitted 2019-08-02 cs.DC

classification cs.DC
keywords performancecomputingdarkparallelizedsequentialupperwallachieved
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The computing performance today is developing mainly using parallelized sequential computing, in many forms. The paper scrutinizes whether the performance of that type of computing has an upper limit. The simple considerations point out that the theoretically possible upper bound is practically achieved, and that the main obstacle to step further is the presently used computing paradigm and implementation technology. In addition to the former "walls", also the "performance wall" must be considered. As the paper points out, similarly to the "dark silicon", also the "dark performance" is always present in the parallelized many-processor systems.

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Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. The need for modern computing paradigm: Science applied to computing

    cs.GL 2019-08 reject novelty 3.0 of 10

    The paper claims that parallelized sequential computing has an inherent efficiency ceiling, and that the EMPA paradigm, using quasi-threads and hardware-software cooperation, can break that ceiling.

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