Near-Memory Computing: Past, Present, and Future

Ahsan Javed Awan; Albert-Jan Boonstra; Gagandeep Singh; Henk Corporaal; Lorenzo Chelini; Roel Jordans; Sander Stuijk; Stefano Corda

REVIEW 4 major objections 5 minor 111 references

Near-Memory Computing: Past, Present, and Future

T0 review · 4 major / 5 minor · reviewed 2026-08-14 · deepseek-v4-flash

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Pith's one-line read Near-memory computing can cut data movement, but the hard part is software.

desk verdict A useful NMC survey with a solid taxonomy, but the forward-looking quantitative claim rests on an idealized, unvalidated analytic model that should be either fixed or explicitly softened before publication. read the letter →

arxiv 1908.02640 v1 pith:F7FTJXZK submitted 2019-08-07 cs.AR cs.DCcs.PF

Gagandeep Singh , Lorenzo Chelini , Stefano Corda , Ahsan Javed Awan , Sander Stuijk , Roel Jordans , Henk Corporaal , Albert-Jan Boonstra This is my paper · ORCID

classification cs.ARcs.DCcs.PF

keywords near-memorycomputingprocessing-in-memorydata-centric3D-stackedmemoryapplicationcharacterizationcompileroffloadinganalyticalperformancemodelwall

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Near-memory computing moves processing into the logic layer of 3D-stacked memory so that data-intensive workloads no longer pay the full cost of shuttling data to the CPU. This paper tries to establish that the decade-old NMC concept is now technologically viable, and that the remaining obstacles are mostly software. It supports that view with a taxonomy organizing the field by memory level, processing-unit type, tooling, interoperability, and application domain, and with a concrete software stack: platform-agnostic metrics for spotting NMC-friendly kernels, a compiler that transparently swaps those kernels for accelerator-library calls, and a first-order analytic model. The model predicts that as L1/L2 miss rates rise, a CPU-centric system falls further behind an NMC system, so the payoff concentrates in low-locality, memory-bound code. A sympathetic reader is left with the conclusion that the key barriers are coherence, virtual memory, programming models, and design-space tooling, not basic hardware feasibility.

What carries the argument

The load-bearing machinery is two-tier. The hardware enabler is the 3D-stacked memory cube, whose DRAM layers sit on a logic layer connected by through-silicon vias, with memory divided into vaults that provide high internal bandwidth. On the software side, the paper's framework rests on four microarchitecture-independent characterization metrics: memory entropy (randomness of the address stream), spatial locality (likelihood of nearby accesses), data-level parallelism per opcode, and basic-block-level parallelism, computed from instruction traces. These metrics let the compiler identify NMC candidates without depending on a specific microarchitecture. The compiler flow extracts kernels in a polyhedral intermediate representation, matches them against a library of accelerator routines, and swaps them in without programmer intervention. The classification table does the organizing work for the survey: every architecture is placed by memory level, processing-unit type and granularity, host, evaluation technique, and the presence or absence of coherence and virtual-memory support, which is what lets the paper locate recurring gaps.

What would settle it

Run the paper's analytic model and a cycle-accurate HMC-style simulator on the same low-locality kernels, replacing the perfect-vault-parallelism assumption with a realistic vault scheduler and row-buffer conflicts. If the simulated NMC delay and energy are not lower than the CPU-centric values whenever L1/L2 miss rates are high, the paper's illustrative claim that low-locality applications benefit from NMC would be overturned.

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Extended reading notes

Core claim

The central claim is that processing 'at the home of data' can substantially reduce the data-movement bottleneck that dominates emerging scale-out workloads with limited data reuse. The paper defends this claim historically and architecturally: 3D stacking with through-silicon vias makes it practical to place programmable, fixed-function, or reconfigurable compute on the memory logic layer, and the survey of prior systems shows the idea has repeatedly delivered performance and energy gains in simulators and prototypes, yet failed to penetrate markets because of earlier technology limits and, now, because of system-software gaps. For the present, the paper contributes a classification scheme covering memory hierarchy, memory type, integration style, NMC unit, implementation granularity, host, evaluation technique, programming model, coherence, virtual memory, and workload. It also presents its own framework: microarchitecture-independent metrics (memory entropy, spatial locality, data-level parallelism, basic-block-level parallelism) to identify NMC-suitable kernels; a compiler that uses a polyhedral intermediate representation and pattern matching to replace detected kernels with accelerator runtime calls; and an analytic model comparing a multicore host with an HMC-like NMC system. The model's illustrative result is that increasing L1 and L2 miss rates degrades the multicore system more than the NMC system in both delay and energy, so low-locality applications benefit from NMC while high-locality applications are better off on the host.

Load-bearing premise

The analytic model assumes that in the NMC case all accesses are made to different vaults inside the HMC memory, that is, perfect vault-level parallelism with no contention, while the CPU-centric alternative is charged with specified L1/L2 miss penalties; if real NMC workloads suffer vault imbalance, row conflicts, or coherence traffic, the modeled advantage shrinks.

Editorial extensions

If this is right

If the framework works as argued, existing C/C++ code can gain NMC acceleration without rewriting, because kernel detection and offloading happen in the compiler.
As cache miss rates climb, the gap between CPU-centric and NMC systems widens in both delay and energy, so NMC's payoff grows exactly where today's data-intensive workloads are worst.
Low-locality kernels such as graph traversal, sparse linear algebra, and streaming analytics are the natural NMC candidates; high-locality kernels should stay on the host.
Widespread NMC adoption depends on solving coherence, virtual memory, data mapping, and programming-model support, since these recur across nearly all surveyed systems.
A standard benchmark suite and open-source simulators are prerequisites for comparing future NMC designs, which the paper identifies as an open gap.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

An editorial extension: the four metrics could be turned into a predictive model, so that a kernel's entropy and spatial-locality scores become a cheap pre-silicon filter for offload decisions; the paper hints at this but does not establish the correlation.
The compiler's pattern-matching approach may generalize to heterogeneous NMC units and to emerging cache-coherent interconnects, potentially allowing NMC to be adopted incrementally in data centers without new programming languages.
The analytic model's assumption of perfect vault-level parallelism means real HMC-style systems with vault imbalance, row conflicts, and coherence traffic may realize a smaller fraction of the modeled gains; a sensitivity study would bound that fraction.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

The survey part of this paper is genuinely useful. The classification scheme in Tables 1–2 is a sensible way to organize the NMC/NDP/PIM literature, and the discussion of challenges—virtual memory, coherence, programming models, data mapping—is accurate at the level a survey should be. The authors also do a fair job of positioning their own work relative to Ghose et al. and other recent surveys. The decision to fold in-storage processing, near-data processing, and PIM under one umbrella is reasonable and makes the paper a good entry point for someone new to the area. Credit is due for being explicit that Section VIII is only a glimpse of their own framework, and for pointing to their earlier papers for details.

The soft spot is exactly what the stress-test note calls out. Section VIII-D's analytic comparison assumes the NMC side has all accesses hitting different HMC vaults, with no bank conflicts, row-buffer misses, vault-controller contention, coherence traffic, or offload overhead, while the CPU side is charged L1/L2 miss penalties. That asymmetry is doing real work: the observation that NMC wins at low locality is partly baked into the assumptions. The model is also under-specified—no equation listing, no parameter table for how vault count or link bandwidth enter the calculation—and it is not validated against any measurement or simulator. Since this is the only quantitative evidence in the paper for NMC's potential, the idealized assumption is load-bearing, not a minor detail.

That said, the authors are more careful than the abstract suggests. The abstract says NMC 'can significantly diminish' data movement, which is a reasonable high-level claim amply supported by the cited literature. In Section VIII-D they call it a first-order early-design model, which is honest. The issue is that Figure 8 and the three bullet observations are stated as if they are findings, not consequences of the modeling assumptions. A short sensitivity discussion or a paragraph acknowledging vault imbalance and coherence costs would largely fix this. Similarly, the compiler flow claims 'completely transparent' offloading, but there is no experimental evaluation in this paper; the claim rests on prior work, which is fine if cited clearly, but the word 'transparent' is doing a lot of work.

Overall, this is a competent survey with a worthwhile taxonomy and a forward-looking section that is a bit too confident relative to its evidence. The citation pattern is appropriate: the authors cite their own earlier papers where those papers are the source of the described tools, which is legitimate. No red flags about invented entities or fabricated results.

Who is this for? Graduate students and researchers entering the NMC area will get real value from the taxonomy and the challenges discussion. The analytic model should not be cited as evidence of NMC benefit without caveats.

Recommendation: Send to peer review. It deserves referee time. The required revisions should focus on Section VIII-D: either add the missing derivation and a sensitivity analysis, or explicitly label the result as illustrative and list the idealizations that could break it. The survey content itself is solid enough to publish after moderate revision.

Referee Report

4 major / 5 minor

Summary. This survey paper organizes the near-memory computing (NMC) literature, proposing a taxonomy by memory hierarchy, processing unit, implementation type, tool support, interoperability, and application domain. It then outlines the authors' own NMC efforts: microarchitecture-independent application characterization metrics, an LLVM/polyhedral-based compiler flow for transparent offloading of NMC kernels, and a first-order analytic model comparing a CPU-centric multicore system with an NMC+host system. The paper argues that NMC can significantly reduce data movement for data-intensive, low-locality workloads, and identifies open challenges including coherence, virtual memory, programming models, and design-space exploration tools.

Significance. If the quantitative claims were fully supported, this paper would be a valuable systematization of the NMC field and a useful position piece on the software and modeling infrastructure needed for NMC adoption. The survey portion is genuinely useful: the taxonomy in Tables 1 and 2 and the discussion of challenges in Section VI synthesize a broad body of work and should serve as a convenient reference. The proposed platform-agnostic characterization metrics and compiler framework are promising ideas that align with the field's need for transparent offloading, though they are not evaluated in this manuscript. The analytic model in Section VIII-D, however, is the only quantitative support for the paper's central claim, and its assumptions are currently too idealized and opaque to sustain the conclusions drawn from it.

major comments (4)

[Section VIII-D, Figure 8] The NMC-vs-CPU comparison is asymmetric and the NMC side is granted an idealized access pattern. The text states, in the 'Performance and Energy Exploration' paragraph, that for the near-memory system 'we consider the scenario when all accesses are done to the different vaults inside the HMC memory,' which effectively gives the NMC system perfect vault-level parallelism, zero bank conflicts, zero row-buffer misses, zero vault-controller contention, and no inter-vault data movement, coherence traffic, or kernel-offload cost. The CPU-centric side, by contrast, is charged with L1/L2 miss penalties through the varied miss rates in Figure 8. As a result, the observations that increasing miss rates degrade the multicore system relative to NMC, and that low-locality applications benefit from NMC, are partly built into the modeling assumptions rather than emerging from empirical or even well-specified quantitative analysis. Because this comparison is the only quantitative evidence for the paper's headline claim, this idealization is load-bearing.
[Section VIII-D, model specification] The analytic model is not presented in a reproducible form. The text describes the performance calculation as 'the ratio between the number of memory accesses required to move the block of data to and from the I/O system and the available I/O bandwidth of each memory subsystem,' but no equations are given, no parameter table lists the access counts, bandwidths, energy values, or how vault count and link count enter the formulas, and no derivation is shown. The energy values (3.7 pJ/b for DRAM, 1.5 pJ/b for logic, 0.96 W static power) are cited to [9] and [37], but the reader cannot verify how these combine with miss rates to produce the normalized delay and energy surfaces in Figure 8. This lack of specification means the model cannot be checked, replicated, or extended by other researchers.
[Section VIII-C, compiler framework] The claimed 'completely transparent' offloading of NMC kernels is not demonstrated. The compiler flow is described in words and in Figure 7, but no experimental results are presented: there are no benchmarks showing that the polyhedral pattern-matching framework detects kernels, that the generated runtime calls are correct, or what performance/energy overhead the offload incurs. Given that the compiler framework is one of the paper's stated contributions, the absence of any evaluation leaves the central claim about transparent NMC adoption unsupported, though it could be addressed by adding experiments or by clearly labeling this section as a research vision.
[Section VIII-B and VIII-D, link between metrics and model] The proposed platform-agnostic metrics (memory entropy, spatial locality, data-level parallelism, basic-block-level parallelism) are not connected to the analytic model. The paper does not specify how a given characterization result, for example the Gramschmidt vs. Jacobi-1d comparison in Figure 6, translates into the miss rates or access-count parameters used in the Section VIII-D comparison. Without this mapping, the characterization metrics and the analytic model remain separate exercises, and the claim that the metrics can 'identify the kernels that can potentially benefit from NMC' is not quantitatively grounded.

minor comments (5)

[Abstract and Section I] The phrase 'significantly diminish the data movement problem' is used as a definitive claim, but the supporting evidence is only the preliminary analytic model; consider softening the wording to 'may diminish' until more validation is available.
[Table 2] The 'NMC Unit' column contains mixed entries (e.g., 'CPU', 'GPU', 'ACC', 'CGRA+FPGA') while the legend in Table 1 defines 'Processing Unit' types; consistency between the column headers and the legend would improve readability.
[Section VII-B, Table 3] Ramulator-PIM [91] is listed with a URL instead of a formal citation, and the 'NMC capabilities' column uses subjective labels ('Yes', 'Limited', 'No') without a definition; a brief explanation of what constitutes 'Limited' would help.
[Section II] In the sentence 'researches have proposed various NMC designs,' 'researches' should be 'researchers'; several other minor typos and grammatical issues (e.g., 'the above mentioned behaviour', 'ofﬂoading') appear throughout, so a careful copyedit is recommended.
[Figure 2] Figure 2 is referenced in Section I but is not described in the text; adding a sentence explaining its content would make the figure self-contained.

Circularity Check

1 steps flagged · score 6.0 of 10

Section VIII-D's NMC-versus-CPU comparison assumes perfect vault-level parallelism and then reports the low-locality NMC advantage as an observation; the result is an artifact of the model's defining premises.

self definitional [Section VIII-D, 'Performance and Energy Exploration' (Figure 8 discussion, pages 11-12)]
"In case of a near-memory system, we consider the scenario when all accesses are done to the different vaults inside the HMC memory, which can exploit the inherent parallelism offered by the 3D memory. ... Based on our evaluation, we make the following three observations. First, ... if the miss rate (L1 and L2) increases the multi-core system performance degrades compared to the NMC systems."

The NMC path is defined as servicing every access through different HMC vaults with no miss penalties, row conflicts, or offload overhead, while the CPU-centric path is charged with L1/L2 miss penalties. The paper's first and third 'observations' — higher miss rates hurt the multicore system relative to NMC, and low-locality applications favor NMC — are direct consequences of that asymmetry, not empirical findings. No equation or measurement is given to show an NMC workload incurring comparable miss or contention costs, so the NMC advantage is inserted as a premise ('all accesses ... to the different vaults') and then reported as a conclusion. The quantitative illustration therefore reduces by construction to the model's own inputs.

full rationale

The survey taxonomy in Sections II-VII is independent and self-contained: it organizes prior NMC architectures under memory-hierarchy, processing-unit, tool, interoperability, and application dimensions, and its classification table is a systematization rather than a prediction. The compiler flow in Section VIII-C is described concretely (LLVM-IR, Polly, Presburger sets, pattern matching) and depends on normal engineering citations rather than on a circular uniqueness claim. The main circularity concern is Section VIII-D: the analytic comparison defines the NMC case as 'all accesses are done to the different vaults inside the HMC memory' and then reports the resulting NMC advantage as an observation. Because the CPU side alone is charged with cache-miss penalties, the conclusion that low-locality, high-miss-rate kernels prefer NMC is true by construction. The paper's broader claim that NMC can diminish data-movement problems is supported by the surveyed literature, so the circularity is partial rather than total; however, the one quantitative demonstration offered by the authors is structurally built from its own favorable assumption.

Assumptions & free parameters 4 free parameters · 4 assumptions · 0 invented entities

The central survey content does not depend on fitted parameters. The illustrative analytic model in Section VIII-D uses hand-chosen device parameters from prior HMC literature and sweeps cache miss rates, but it is not validated against real or simulated systems. The compiler framework assumes an accelerator library and pattern-matching capability that are not demonstrated.

free parameters (4)

HMC DRAM layer energy per bit = 3.7 pJ/b
Taken from HMC references [9] and [37]; central to the energy comparison in Section VIII-D.
HMC logic layer energy per bit = 1.5 pJ/b
Assumed for operations in the logic layer; used in the NMC energy model.
HMC logic layer static power = 0.96 W
Assumed from Pugsley et al. [37] to model added logic; used in static energy estimates.
NMC core frequency = 1.2 GHz
Chosen for the low-power cores in the logic layer (Table 4); affects execution time estimates.

assumptions (4)

domain assumption Data movement is a dominant bottleneck for data-intensive applications
Motivates the whole paper (Introduction); likely true but not proven here.
domain assumption 3D-stacked memory with a logic layer provides sufficient bandwidth and energy efficiency for near-memory compute units
Assumed from HMC/HBM literature, e.g., [9]-[12]; underlies the NMC promise.
domain assumption Near-memory accelerators expose a library of memory-bound kernels via an API that the compiler can match
Stated in Section VIII-C; the compiler flow depends on this library existing.
domain assumption The HMC vault model with all accesses spread across vaults represents the NMC execution scenario
Section VIII-D idealizes the NMC memory system; if real workloads cause vault contention, the performance/energy advantage is overstated.

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Cite this review

Pith. "Pith review of Near-Memory Computing: Past, Present, and Future." pith.science (2026). https://pith.science/paper/F7FTJXZK

@misc{pith2026190802640,
  author       = {Pith},
  title        = {Pith review of: Near-Memory Computing: Past, Present, and Future},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/F7FTJXZK}},
  note         = {Machine review of arXiv:1908.02640}
}

read the original abstract

The conventional approach of moving data to the CPU for computation has become a significant performance bottleneck for emerging scale-out data-intensive applications due to their limited data reuse. At the same time, the advancement in 3D integration technologies has made the decade-old concept of coupling compute units close to the memory --- called near-memory computing (NMC) --- more viable. Processing right at the "home" of data can significantly diminish the data movement problem of data-intensive applications. In this paper, we survey the prior art on NMC across various dimensions (architecture, applications, tools, etc.) and identify the key challenges and open issues with future research directions. We also provide a glimpse of our approach to near-memory computing that includes i) NMC specific microarchitecture independent application characterization ii) a compiler framework to offload the NMC kernels on our target NMC platform and iii) an analytical model to evaluate the potential of NMC.

Figures

Figures reproduced from arXiv: 1908.02640 by the authors.

**Figure 2.** Processing options in the memory hierarchy high [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗

**Figure 3.** Micron’s Hybrid Memory Cube (HMC) [10] com [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗

Figures from the paper (5 more)

**Figure 4.** Figure 4: Design space exploration highlighting application [PITH_FULL_IMAGE:figures/full_fig_p009_4.png]

**Figure 5.** Figure 5: Overview of a system with NMC capability [83]. [PITH_FULL_IMAGE:figures/full_fig_p010_5.png]

**Figure 6.** Figure 6: Spatial Locality and Memory Entropy characteri [PITH_FULL_IMAGE:figures/full_fig_p011_6.png]

**Figure 7.** Figure 7: Proposed compilation flow for the system with NMC capabilities depicted in Figure 5. [PITH_FULL_IMAGE:figures/full_fig_p012_7.png]

**Figure 8.** Figure 8: Performance and energy comparison between multi-core and an NMC system, which is attached to a host [PITH_FULL_IMAGE:figures/full_fig_p012_8.png]

Discussion (0). Continue with ORCID to comment.

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