High resolution digitization system for the CROSS experiment

C. Gotti; G. Pessina; P. Carniti

REVIEW 3 major objections 5 minor 10 references

High resolution digitization system for the CROSS experiment

T0 review · 3 major / 5 minor · reviewed 2026-08-14 · deepseek-v4-flash

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Pith's one-line read A custom 12-channel digitizer board for the CROSS bolometer experiment reaches an effective resolution of 22.0 bits at 1 ksps, 21.1 bits at 5 ksps, and 19.7 bits at 25 ksps, corresponding to 4.7 µV, 9.2 µV, and 24 µV RMS input noise.

desk verdict A credible, well-scoped characterization of a custom 12-channel DAQ board for bolometric experiments; the headline resolution numbers are real for single boards, but system-level claims are honestly deferred. read the letter →

arxiv 1908.11242 v2 pith:FH74SVRF submitted 2019-08-29 physics.ins-det

P. Carniti , C. Gotti , G. Pessina This is my paper · ORCID

classification physics.ins-det

keywords dataacquisitionsystemhighresolutiondigitizationbolometricexperimentneutrinolessdouble-betadecayanti-aliasingfilterdelta-sigmaADCFPGAreadoutUDPtransfer

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper reports the design and measured performance of a custom 12-channel digitizer board for the CROSS bolometric experiment, which searches for neutrinoless double-beta decay. The central result is a measured effective resolution of 22.0 bits at 1 ksps, 21.1 bits at 5 ksps, and 19.7 bits at 25 ksps, corresponding to 4.7 µV, 9.2 µV, and 24 µV RMS noise respectively. At the experiment's typical 5 ksps rate this exceeds the ~20-bit target, and the board's anti-aliasing filter cutoff can be digitally set from 24 Hz to 2.5 kHz for each detector. With one FPGA collecting 96 channels from eight boards and sending data over Ethernet via UDP, the system scales to the full experiment. If the bench performance carries over, CROSS can run continuous high-resolution acquisition with the speed and pulse-shape discrimination its physics requires.

What carries the argument

The load-bearing element is the per-channel signal chain on each 12-channel board: a buffered input that can be grounded for offset self-calibration, a 6-pole Bessel-Thomson anti-aliasing filter whose cutoff frequency is set by a 10-bit digital trimmer over 24 Hz to 2.5 kHz, a conversion to differential, and a dual-channel 24-bit delta-sigma ADC. The tunable filter is what allows one board design to serve both slow and fast bolometers, and the delta-sigma ADC is what provides the high effective resolution at the low sample rates used. The back end, a commercial FPGA module that reads six 20 MHz SPI lines and transmits via synthesized UDP over Ethernet, is the mechanism that scales the 12-channel board to 96 channels per FPGA.

What would settle it

Assemble the final backplane with eight DAQ boards and one FPGA, digitize all 96 channels at 5 ksps continuously while transferring the full UDP data stream to a storage server, and measure each channel's input-referred noise; if the effective resolution drops below roughly 20 bits or data packets are lost at the full rate, the scalability and performance claims for the complete system fail.

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Extended reading notes

Core claim

The central discovery is that a DAQ board combining a low-noise analog front end, a 6-pole Bessel-Thomson anti-aliasing filter with a 10-bit digitally selectable cutoff (24 Hz to 2.5 kHz), and 24-bit delta-sigma ADCs reaches an effective resolution of 22.0 bits at 1 ksps, 21.1 bits at 5 ksps, and 19.7 bits at 25 ksps, or 4.7 µV, 9.2 µV, and 24 µV RMS input noise. Above 5 ksps the resolution is dominated by the ADC and its buffer; the analog section alone contributes 5.7–7.1 µV RMS. The board reads out in both analog and digital modes, and in the digital mode an FPGA collects eight boards (96 channels) over 20 MHz SPI lines and forwards the data over 1 Gbps Ethernet using a hardware-synthesized UDP protocol. The measured offset drift is 10 µV/°C and gain drift 10 ppm/°C, meeting the stability needs of a long-running underground experiment.

Load-bearing premise

The measured resolution was obtained on first sample boards in a lab test with direct FPGA readout, and the full multi-board system streaming 96 channels through the UDP Ethernet link has not yet been built, so the claimed performance must carry over from the single board to the complete configuration.

Editorial extensions

If this is right

CROSS can run continuous acquisition at 5 ksps per channel with effective resolution above 21 bits, meeting the noise and pile-up requirements for pulse-shape discrimination.
One FPGA handles eight boards (96 channels), so the full detector array can be read out with a small number of standard Ethernet links.
The digitally selectable filter cutoff lets the same board be tuned per detector, from 24 Hz for slow bolometers to 2.5 kHz for fast scintillating ones.
In 6-channel mode the same hardware digitizes at 250 ksps per channel, making the board usable for faster-signal applications without change.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

Because the noise above 5 ksps is dominated by the ADC stage, a lower sampling rate than 1 ksps may push effective resolution beyond 22 bits, which could benefit other precision measurements with very slow signals.
The same board architecture, if ported or reproduced, would likely satisfy the DAQ needs of other bolometric double-beta experiments that require continuous acquisition and per-channel filter tuning.
The paper's single-board characterization leaves open whether the FPGA and UDP link add digital noise or packet loss at full load; a natural test extension is to compare the reconstructed noise spectrum with and without the Ethernet link active.
The offset self-calibration via grounded inputs suggests the board could self-correct long-term drifts in hardware, a feature that might remove the need for frequent baseline calibrations in a multi-year run.

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Signed reviews

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

You should know this is a straightforward hardware paper, not a physics result. It describes a 12-channel DAQ board for the CROSS bolometric experiment, with 24-bit delta-sigma ADCs and a digitally programmable 6-pole Bessel-Thomson filter. The measurements are direct and credible: transfer functions from a spectrum analyzer, CMRR, analog noise spectra, and effective resolution from digitized data. The effective resolution numbers (22.0 bits at 1 ksps, 21.1 at 5 ksps, 19.7 at 25 ksps) line up with the reported RMS noise and the ADC's expected behavior. Temperature stability (10 uV/C offset, 10 ppm/C gain) is a nice extra.

What is new is not any single component but the integration: 12 channels per board, 10-bit cutoff selection from 24 Hz to 2.5 kHz for fast scintillating bolometers, and an FPGA/UDP readout path designed for scalability. The paper is honest about what is tested and what is not. Section 4 explicitly says the full backpanel 'will be designed' and that qualification at full data rate with multiple boards is future work. So the stress-test concern about multi-board noise is real, but the paper does not overclaim it: the resolution values are presented as single-board results.

Soft spots: no error bars on any measurement, which is typical for this kind of paper but still limits comparisons. The input full-scale range is unstated, so you can't easily convert microvolts RMS to ppm of full scale. The claim of 'many improvements over widely used commercial solutions' is asserted without a quantitative baseline, which is a minor sin. Also, the tests are on 'first samples,' so board-to-board variation is unknown. None of this undermines the central single-board result.

Who it is for: people designing DAQ for low-temperature detectors, and CROSS collaborators. It is a competent contribution to a niche literature and deserves a serious referee; the measurements are reproducible and the design is clearly documented. I would accept it for peer review without hesitation. If the journal allows, I would ask the authors to add error bars, specify the input full-scale range, and soften the comparison to commercial systems until the side-by-side test they mention actually happens.

Referee Report

3 major / 5 minor

Summary. The paper describes the design and characterization of a custom 12-channel DAQ board for the CROSS bolometric neutrinoless-double-beta-decay experiment. Each channel has a 6-pole Bessel-Thomson anti-aliasing filter with 10-bit digitally selectable cutoff from 24 Hz to 2.5 kHz, followed by a dual-channel 24-bit delta-sigma ADC. A commercial FPGA module collects data from 8 boards (96 channels) over 20 MHz SPI and sends it over UDP Ethernet. The measured performance includes the filter transfer function, DC CMRR of about -70 dB, analog noise of 5.7-7.1 uV RMS, effective resolution of 22.0/21.1/19.7 bits at 1/5/25 ksps (corresponding to 4.7/9.2/24 uV RMS), and temperature drifts of 10 uV/C and 10 ppm/C for offset and gain. The authors state that the full multi-board backpanel is still to be designed and that multi-board operation at full data rate has not yet been tested.

Significance. If the reported single-board performance transfers to the final system, the board meets CROSS's requirement for continuous, high-resolution digitization at 5 ksps with 12 channels per board, and it offers a useful design reference for other bolometric experiments. The strengths of the work are that the central figures come from direct measurements against external instruments (spectrum analyzer, climatic chamber) and involve no fitted parameters or circular self-calibration. The analog filter design and the temperature-stability measurements are concrete and reproducible. However, the headline effective-resolution numbers are presented without a stated full-scale range or measurement statistics, and the system-level claim in the title/abstract goes beyond what has actually been measured: only single-board operation with a provisional backpanel is characterized.

major comments (3)

[Section 3, 'Board performance'] The central performance claim is the effective resolution (22.0/21.1/19.7 bits at 1/5/25 ksps, corresponding to 4.7/9.2/24 uV RMS), but the input full-scale range is never stated. Effective resolution in bits is a ratio of full-scale range to RMS noise, and the quoted numbers imply a full-scale range of roughly 20 V_pp (approximately +/-10 V). Please state explicitly the full-scale input range, the formula used for effective bits, and the bandwidth over which the RMS noise values are computed; without this, the headline numbers cannot be reproduced or compared with other systems.
[Section 4, 'Conclusions and future developments'] The title and abstract describe a digitization system spanning 8 boards per FPGA and UDP transfer at up to 768 Mbps, but all quantitative performance figures come from first sample boards read out through a provisional backpanel. Section 4 states that the full backpanel 'will be designed' and that multi-board operation at full data rate is future work. No crosstalk measurement, simultaneous-channel noise measurement, or end-to-end SPI/UDP data-rate test is reported. The abstract and conclusions should therefore be explicitly scoped as single-board characterization, with the multi-board data-rate path stated as an untested assumption; otherwise the system-level resolution claim rests on the unverified premise that the FPGA/UDP readout adds no additional noise or crosstalk.
[Section 3, Table 1 and effective-resolution paragraph] No measurement statistics are provided for the central figures: the number of boards or channels characterized, the number of repeated acquisitions, or the channel-to-channel spread in effective resolution, CMRR, or temperature drift. The reported values are single numbers with no uncertainty or spread, which makes it difficult to judge whether the performance is representative. Please report at least the sample size and the observed spread across channels for the effective resolution at 5 ksps, the operating point most relevant to CROSS.

minor comments (5)

[Abstract and Section 3] The abstract says 'effective resolution of 21 bits at the typical sample rate' while Section 3 reports 21.1 bits; please align the rounding or state the values consistently.
[Section 2, Figure 3] There is a typographical double period in 'Fig.. 3 shows'; also, the caption of Figure 3 could state the cutoff-frequency range and the digital trimmer resolution so the reader does not have to search the text.
[Section 3, Figure 7] The analog noise values in Figure 7 are quoted over a 0.1 Hz-100 kHz bandwidth, while digitized data at 5 ksps necessarily covers a narrower Nyquist band; please clarify the measurement bandwidth for each curve so that the comparison between analog and digitized noise is meaningful.
[Section 4] The claim that the board improves on commercial solutions in 'noise, stability and power consumption' is not supported by any quantitative comparison or citation in the manuscript; either add the comparison or soften the claim.
[Section 2, back-end description] The description of the Ethernet link as 'optically decoupled' is unclear because a standard 1 Gbps Ethernet PHY is not normally optically decoupled; please clarify the actual galvanic-isolation scheme between the FPGA/backpanel and the storage system.

Circularity Check

0 steps flagged · score 0.0 of 10

No circular reasoning: all headline results are direct laboratory measurements against external instruments, not derived from fitted parameters or self-citations.

full rationale

The paper is an instrumentation report whose central claims are empirical measurements: effective resolution (22.0/21.1/19.7 bits at 1/5/25 ksps), analog noise (5.7–7.1 uV RMS), CMRR (−70 dB), and temperature drifts (10 uV/C and 10 ppm/C). These quantities are obtained with test equipment (Agilent 4395A spectrum analyzer, climatic chamber, digitized readout) and are not derived from any model parameter fitted to the same data. There is no equation in which an output is defined as an input, no fitted parameter renamed as a prediction, and no uniqueness theorem invoked. The only caveat, explicit in Sec. 4, is that the full 96-channel multi-board FPGA/UDP configuration 'will be designed' after a prototype detector test; this is a scalability assumption, not a circular step. The cited references (CROSS, CUORE, CUPID-0, Nones et al.) provide experimental context and prior bolometric results but do not carry the paper's own measured performance claims. No self-citation is used as load-bearing evidence for the quoted resolution numbers. Therefore the paper is self-contained against external benchmarks and exhibits no significant circularity.

Assumptions & free parameters 0 free parameters · 2 assumptions · 0 invented entities

The paper reports empirical measurements and does not fit any parameters. It relies on standard laboratory measurement assumptions and on the representativeness of the tested boards.

assumptions (2)

domain assumption The measurement equipment (Agilent 4395A spectrum analyzer and climate chamber) is correctly calibrated and the reported noise and transfer function values are accurate.
Section 3 uses these instruments without detailing calibration or uncertainty.
domain assumption The performance measured on the first board samples is representative of all boards.
Section 3: 'The first samples of the board have been fully characterized'; no board-to-board variation is discussed.

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Cite this review

Pith. "Pith review of High resolution digitization system for the CROSS experiment." pith.science (2026). https://pith.science/paper/FH74SVRF

@misc{pith2026190811242,
  author       = {Pith},
  title        = {Pith review of: High resolution digitization system for the CROSS experiment},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/FH74SVRF}},
  note         = {Machine review of arXiv:1908.11242}
}

read the original abstract

The signal digitization for CROSS, a bolometric experiment for the search of neutrinoless double beta decay at LSC - Canfranc Underground Laboratory, will be based on a custom solution comprised of an analog-to-digital board interfaced to an Altera Cyclone V FPGA module. Each analog-to-digital board hosts 12 channels that allow data digitization up to 25 ksps per channel and an effective resolution of 21 bits at the typical sample rate required by the experiment (5 ksps). The board also allows to digitally select the cut-off frequency of the anti-aliasing filter with 10 bit resolution from 24 Hz up to 2.5 kHz, as required by fast scintillating bolometers. The FPGA is responsible for the synchronization of the analog-to-digital boards and for the data transfer to the storage, using UDP protocol on a standard Ethernet interface. Each FPGA can manage the data coming from 8 boards (96 channels), allowing an excellent scalability. In this contribution we will present a complete overview of the system, and a detailed characterization of the system performance.

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

10 extracted references · 3 canonical work pages

[1]

I. C. Bandac et al., The 0 2 -decay CROSS experiment: preliminary results and prospects, arXiv:1906.10233 (2019)

work page Pith review arXiv 2019
[2]

Alduino, First Results from CUORE: A Search for Lepton Number Violation via 0 Decay of ^ 130 Te , Phys

C. Alduino, First Results from CUORE: A Search for Lepton Number Violation via 0 Decay of ^ 130 Te , Phys. Rev. Lett. 120 (2018) 132501, DOI: 10.1103/PhysRevLett.120.132501

work page doi:10.1103/physrevlett.120.132501 2018
[3]

Nones et al., Superconducting Aluminum Layers as Pulse Shape Modifiers: An Innovative Solution to Fight Against Surface Background in Neutrinoless Double Beta Decay Experiments, J

C. Nones et al., Superconducting Aluminum Layers as Pulse Shape Modifiers: An Innovative Solution to Fight Against Surface Background in Neutrinoless Double Beta Decay Experiments, J. Low Temp. Phys. 167 (2012) 1029–1034, DOI: 10.1007/s10909-012-0558-y

work page doi:10.1007/s10909-012-0558-y 2012
[4]

Azzolini, First Result on the Neutrinoless Double- Decay of ^ 82 Se with CUPID-0 , Phys

O. Azzolini, First Result on the Neutrinoless Double- Decay of ^ 82 Se with CUPID-0 , Phys. Rev. Lett. 120 (2018) 232502, DOI: 10.1103/PhysRevLett.120.232502

doi:10.1103/physrevlett.120.232502 2018
[5]

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Show all 10 references

[9]

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Pith tools

Reviewed August 14, 2026 · model on record in the stance chip above.

[1] [1]

I. C. Bandac et al., The 0 2 -decay CROSS experiment: preliminary results and prospects, arXiv:1906.10233 (2019)

work page Pith review arXiv 2019

[2] [2]

Alduino, First Results from CUORE: A Search for Lepton Number Violation via 0 Decay of ^ 130 Te , Phys

C. Alduino, First Results from CUORE: A Search for Lepton Number Violation via 0 Decay of ^ 130 Te , Phys. Rev. Lett. 120 (2018) 132501, DOI: 10.1103/PhysRevLett.120.132501

work page doi:10.1103/physrevlett.120.132501 2018

[3] [3]

Nones et al., Superconducting Aluminum Layers as Pulse Shape Modifiers: An Innovative Solution to Fight Against Surface Background in Neutrinoless Double Beta Decay Experiments, J

C. Nones et al., Superconducting Aluminum Layers as Pulse Shape Modifiers: An Innovative Solution to Fight Against Surface Background in Neutrinoless Double Beta Decay Experiments, J. Low Temp. Phys. 167 (2012) 1029–1034, DOI: 10.1007/s10909-012-0558-y

work page doi:10.1007/s10909-012-0558-y 2012

[4] [4]

Azzolini, First Result on the Neutrinoless Double- Decay of ^ 82 Se with CUPID-0 , Phys

O. Azzolini, First Result on the Neutrinoless Double- Decay of ^ 82 Se with CUPID-0 , Phys. Rev. Lett. 120 (2018) 232502, DOI: 10.1103/PhysRevLett.120.232502

doi:10.1103/physrevlett.120.232502 2018

[5] [5]

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[7] [7]

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