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A Hardware-Aware Heuristic for the Qubit Mapping Problem in the NISQ Era

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arxiv 2010.03397 v1 pith:KRGR4FRV submitted 2020-10-06 cs.AR quant-ph

classification cs.ARquant-ph
keywords quantumhardwarecircuitnisqconnectivityfidelityhardware-awaremapping
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Due to several physical limitations in the realisation of quantum hardware, today's quantum computers are qualified as Noisy Intermediate-Scale Quantum (NISQ) hardware. NISQ hardware is characterized by a small number of qubits (50 to a few hundred) and noisy operations. Moreover, current realisations of superconducting quantum chips do not have the ideal all-to-all connectivity between qubits but rather at most a nearest-neighbour connectivity. All these hardware restrictions add supplementary low-level requirements. They need to be addressed before submitting the quantum circuit to an actual chip. Satisfying these requirements is a tedious task for the programmer. Instead, the task of adapting the quantum circuit to a given hardware is left to the compiler. In this paper, we propose a Hardware-Aware mapping transition algorithm (HA) that takes the calibration data into account with the aim to improve the overall fidelity of the circuit. Evaluation results on IBM quantum hardware show that our HA approach can outperform the state of the art both in terms of the number of additional gates and circuit fidelity.

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Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Physics-Aware Compilation for Parallel Quantum Circuit Execution on Neutral Atom Arrays

    quant-ph 2025-05 conditional novelty 6.0 of 10

    Physics-Aware Compilation (PAC) speeds up neutral atom quantum circuit compilation by partitioning both the hardware plane and the circuit graph, achieving up to 202.81x faster solving than DPQA with comparable circuit depth.

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