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Wafer-scale integration of graphene-based photonic devices

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arxiv 2012.05816 v2 pith:OSQ5ID5H submitted 2020-11-18 physics.app-ph cond-mat.mtrl-sciphysics.optics

classification physics.app-phcond-mat.mtrl-sciphysics.optics
keywords devicedevicesflowgraphenephotonicfabricationgraphene-basedgrowth
verification ladder T0 review T1 audit T2 compute T3 formal
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Graphene and related materials can lead to disruptive advances in next generation photonics and optoelectronics. The challenge is to devise growth, transfer and fabrication protocols providing high (>5,000 cm2 V-1 s-1) mobility devices with reliable performance at the wafer scale. Here, we present a flow for the integration of graphene in photonics circuits. This relies on chemical vapour deposition (CVD) of single layer graphene (SLG) matrices comprising up to ~12000 individual single crystals (SCs), grown to match the geometrical configuration of the devices in the photonic circuit. This is followed by a transfer approach which guarantees coverage over ~80% of the device area, and integrity for up to 150 mm wafers, with room temperature mobility ~5000 cm2 V-1 s-1. We use this process flow to demonstrate double SLG electro-absorption modulators with modulation efficiency ~0.25, 0.45, 0.75, 1 dB V-1 for device lengths ~30, 60, 90, 120 {\mu}m. The data rate is up to 20 Gbps. Encapsulation with single-layer hBN is used to protected SLG during plasma-enhanced CVD of Si3N4, ensuring reproducible device performance. Our full process flow (from growth to device fabrication) enables the commercial implementation of graphene-based photonic devices.

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