Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links
Paper Citation Record · LEDGER
Demystifying the Nvidia Ampere Architecture through Microbenchmarking and Instruction-level Analysis
As of 10 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 3 inbound Pith citation observations for arXiv:2208.11174.
A citation records a reference. It does not transfer a finding from one paper to another.
Coverage vector
One-hop event checks from named stored sources.
Source: scholarly_work_events, retraction_status_cache, observed 2026-08-10T06:31:04.303077+00:00
Pith citing papers itemized under the disclosed page cap.
Source: paper_references, paper_reference_links, observed 2026-08-08T20:44:48.392762Z
A source-named dated measurement, never combined with another source.
Source: arxiv_reference, observed 2026-06-28T20:32:37.991874Z
Reference resolution
0 of 0 outbound references displayed
- verified exact0
- verified fuzzy0
- unresolved0
- parse uncertain0
- malformed identifier0
- metadata mismatch0
External citation measurements
No source-named external measurement is stored.
Outbound references
No outbound reference observations are available for this paper version.
Pith citing papers
Observation 48ce5bd3-1114-4109-9ed5-56510e59bed9 · inbound
QuEST: Stable Training of LLMs with 1-Bit Weights and Activations cites this paper.
QuEST: Stable Training of LLMs with 1-Bit Weights and Activations Demystifying the Nvidia Ampere Architecture through Microbenchmarking and Instruction-level Analysis
Reference 2022
- Resolution
- unresolved
- no resolver link, observed 2026-08-08T20:44:48.392762Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 0e8a28ad-273f-4be0-beee-ec0f50889c3e · inbound
Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures cites this paper.
Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Demystifying the Nvidia Ampere Architecture through Microbenchmarking and Instruction-level Analysis
Reference 2
- Resolution
- verified exact
- arxiv_id, observed 2026-06-28T20:32:37.993466Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.
Observation ba02d514-9b0d-4236-9713-264ed07818bb · inbound
Incast-Free MoE Rate-Based Scheduling cites this paper.
Incast-Free MoE Rate-Based Scheduling Demystifying the Nvidia Ampere Architecture through Microbenchmarking and Instruction-level Analysis
Reference 6
- Resolution
- unresolved
- no resolver link, observed 2026-08-01T00:15:00.478533Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.