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PRESERVE: Prefetching Model Weights and KV-Cache in Distributed LLM Serving

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arxiv 2501.08192 v2 pith:22TNDKQD submitted 2025-01-14 cs.AI cs.ARcs.DC

classification cs.AIcs.ARcs.DC
keywords communicationperformancepreserveacceleratorscachecostdevicesinference
verification ladder T0 review T1 audit T2 compute T3 formal
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Large language models (LLMs) are typically served from clusters of GPUs/NPUs that consist of large number of devices. Unfortunately, communication between these devices incurs significant overhead, increasing the inference latency and cost while limiting the scalability. Prior work addressed this issue by overlapping communication with compute, but has severe limitations due to the data dependencies between these operations. In this paper, we propose PRESERVE, a novel framework that prefetches model weights and KV-cache from off-chip HBM memory to the on-chip cache of AI accelerators during the communication operations, which offers various advantages and performance improvements compared to prior methods. Through extensive experiments conducted on commercial AI accelerators, we demonstrate up to 1.6x end-to-end speedup on state-of-the-art, open-source LLMs. Additionally, we perform a design space exploration that identifies the optimal hardware configuration for the proposed method, showing a further 1.25x improvement in performance per cost by selecting the optimal L2 cache size. Our results show that PRESERVE has the potential to mitigate the memory bottlenecks and communication overheads, offering a solution to improve the performance and scalability of the LLM inference systems.

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Forward citations

Cited by 3 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. SiFAR: Synchronization-Free All-Reduce for Low-Latency LLM Inference

    cs.DC 2026-07 accept novelty 6.5 of 10

    SiFAR cuts All-Reduce latency up to 52% and end-to-end decode throughput up to 18.6% at TP=8 by dual buffering, in-switch redundant pull, and speculative reduction with validation.

  2. A Distributed Learned Hash Table

    cs.NI 2025-08 conditional novelty 6.0 of 10

    A learned order-preserving hash inside a Chord-style DHT lets range queries finish in roughly the same cost as single-key lookups, cutting latency and messages by 80-90%+ in tests.

  3. Architecting Long-Context LLM Acceleration with Packing-Prefetch Scheduler and Ultra-Large Capacity On-Chip Memories

    cs.AR 2025-08 unverdicted novelty 5.0 of 10

    Co-designing a packing-prefetch scheduler with an ultra-large 512 MB monolithic 3D BEOL on-chip memory is claimed to reduce KV-cache transfer bottlenecks, yielding 8.06x decode speedup and 1.5x to 2.4x HBM bandwidth c...

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