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BP-NTT: Fast and Compact in-SRAM Number Theoretic Transform with Bit-Parallel Modular Multiplication
Hardware Architecture · Submitted 1 Mar 2023
abstract compiled · 2026-09-23 · no language-model review
The authors' main claim By leveraging an optimized bit-parallel modular multiplication and introducing costless shift operations, our proposed solution provides up to 29x higher throughput-per-area and 2.8-100x better throughput-per-area-per-joule compared to the state-of-the-art.
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The abstract, sentence by sentence
Number Theoretic Transform (NTT) is an essential mathematical tool for computing polynomial multiplication in promising lattice-based cryptography. However, costly division operations and complex data dependencies make efficient and flexible hardware design to be challenging, especially on resource-constrained edge devices. Existing approaches either focus on only limited parameter settings or impose substantial hardware overhead. In this paper, we introduce a hardware-algorithm methodology to efficiently accelerate NTT in various settings using in-cache computing. By leveraging an optimized bit-parallel modular multiplication and introducing costless shift operations, our proposed solution provides up to 29x higher throughput-per-area and 2.8-100x better throughput-per-area-per-joule compared to the state-of-the-art.
background contribution method result interpretation main claim
| # | sentence | role | the authors' own work | states the main conclusion | strength |
|---|---|---|---|---|---|
| s0 | Number Theoretic Transform (NTT) is an essential mathematical tool for computing polynomial multiplication in promising lattice-based cryptography. | background 1.00 | 0.04 | 0.02 | asserted 1.00 |
| s1 | However, costly division operations and complex data dependencies make efficient and flexible hardware design to be challenging, especially on resource-constrained edge devices. | background 0.81 | 0.07 | 0.02 | asserted 0.99 |
| s2 | Existing approaches either focus on only limited parameter settings or impose substantial hardware overhead. | gap 0.92 | 0.04 | 0.02 | asserted 1.00 |
| s3 | In this paper, we introduce a hardware-algorithm methodology to efficiently accelerate NTT in various settings using in-cache computing. | contribution 0.99 | 0.88 | 0.16 | asserted 1.00 |
| s4 | By leveraging an optimized bit-parallel modular multiplication and introducing costless shift operations, our proposed solution provides up to 29x higher throughput-per-area and 2.8-100x better throughput-per-area-per-joule compared to the state-of-the-art. | result 0.97 | 0.94 | 0.86 | asserted 0.99 |
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The paper
Original abstract
Number Theoretic Transform (NTT) is an essential mathematical tool for computing polynomial multiplication in promising lattice-based cryptography. However, costly division operations and complex data dependencies make efficient and flexible hardware design to be challenging, especially on resource-constrained edge devices. Existing approaches either focus on only limited parameter settings or impose substantial hardware overhead. In this paper, we introduce a hardware-algorithm methodology to efficiently accelerate NTT in various settings using in-cache computing. By leveraging an optimized bit-parallel modular multiplication and introducing costless shift operations, our proposed solution provides up to 29x higher throughput-per-area and 2.8-100x better throughput-per-area-per-joule compared to the state-of-the-art.
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How the literature uses it
2 arXiv papers cite this in 6 sentences
Papers citing it · 3 sentences without a confident label
Compares with it 1 paper
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Radix-4 and overflow LUTs require a total of 13 WLs, but they can be reused for multiple iterations and for multiple calculations, thus not considered intermediate results. <Ref> shows the memory utilization comparison for operand storage and intermediate of our work along with existing SRAM PIMs [ref] .
ModSRAM: Algorithm-Hardware Co-Design for Large Number Modular Multiplication in SRAM · Memory Utilization · 0.97
Cites it as background 1 paper
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Recently, there have been many cryptographic PIM accelerators in SRAM [ref] and ReRAM [ref] that tried to compute cryptographic schemes in/near-memory.
ModSRAM: Algorithm-Hardware Co-Design for Large Number Modular Multiplication in SRAM · Cryptographic PIM · 0.95
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