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Exploration and Exploitation of Hidden PMU Events
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Performance Monitoring Unit (PMU) is a common hardware module in Intel CPUs. It can be used to record various CPU behaviors therefore it is often used for performance analysis and optimization. Of the 65536 event spaces, Intel has officially published only 200 or so. In this paper, we design a hidden PMU event collection method. And we found a large number of undocumented PMU events in CPUs of Skylake, Kabylake, and Alderlake microarchitectures. We further demonstrate the existence of these events by using them for transient execution attack detection and build-side channel attacks. This also implies that these hidden PMU events have huge exploitation potential and security threats.
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A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs
A centralized EVU-APMU hardware architecture collects and processes performance counter data on a dedicated side processor, demonstrated on a RISC-V SoC for memory regulation and function-level profiling.
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