Hardware-Efficient Quantum Random Access Memory Design with a Native Gate Set on Superconducting Platforms

Quantum Random Access Memory (QRAM) is a critical component for enabling data queries in superposition, which is the cornerstone of quantum algorithms. Among various QRAM architectures, the bucket-brigade model stands out due to its noise resilience. This paper presents a hardware-efficient native gate set {iSCZ, C-iSCZ} for implementing bucket-brigade QRAM on superconducting platforms. The experimental feasibility of the proposed gate set is demonstrated, showing high fidelity and reduced complexity. By leveraging the complementary control property in QRAM, our approach directly substitutes the conventional {SWAP, CSWAP} gates with the new gate set, eliminating decomposition overhead and significantly reducing circuit depth and gate count.