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Efficient Magic State Distillation by Zero-Level Distillation

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arxiv 2403.03991 v2 pith:77ABPU6G submitted 2024-03-06 quant-ph

classification quant-ph
keywords distillationmagicstateerrorlogicalphysicalratelevel
verification ladder T0 review T1 audit T2 compute T3 formal
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abstract

Magic state distillation (MSD) is an essential element for universal fault-tolerant quantum computing, which distills a high-fidelity magic state from noisy magic states using ideal (error-corrected) Clifford operations. For ideal Clifford operations, it needs to be performed on the logical qubits and hence incurs a large spatiotemporal overhead, which is one of the major bottlenecks for the realization of fault-tolerant quantum computers (FTQCs). Here we propose zero-level distillation, which prepares a high-fidelity logical magic state at the physical level, namely zero level, using physical qubits and nearest-neighbor two-qubit gates on a square lattice. We develop a zero-level distillation circuit and show that distillation can be made even more efficient than the conventional sophisticated approaches with logical level distillations. The key idea involves the Knill et al.-type distillation using the Steane code and its careful mapping to the square-lattice architecture with error detection. The distilled magic state on the Steane-code state is then teleported or converted to surface codes. We numerically find that the error rate of the logical magic state scales as approximately $100 \times p^{2}$ in terms of the physical error rate $p$. For example, with a physical error rate of $p = 10^{-4}$ ($10^{-3}$), the logical error rate is reduced to $p_{L} = 10^{-6}$ ($10^{-4}$), resulting in an improvement of 2 (1) orders of magnitude. This contributes to reducing both space and time overhead for early FTQC as well as full-fledged FTQC combined with conventional multilevel distillation protocols.

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Cited by 2 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. The Pangaea Architecture: Fault-Tolerant Heterogeneous Topological Codes via a Quantum Bus

    quant-ph 2026-08 conditional novelty 7.0 of 10

    A quantum bus connects many logical qubits through a gauge-code strip, with a claimed factor O(d) reduction in qubit overhead for long-range logical interactions.

  2. Synchronization for Fault-Tolerant Quantum Computers

    quant-ph 2025-06 conditional novelty 5.0 of 10

    Active and Hybrid synchronization policies cut logical error rates by up to 2.4x and 3.4x compared to passive waiting, by distributing idle time across syndrome generation rounds.

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