Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links
Paper Citation Record · LEDGER
Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework
As of 8 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 1 inbound Pith citation observation for arXiv:2403.11202.
A citation records a reference. It does not transfer a finding from one paper to another.
Coverage vector
One-hop event checks from named stored sources.
Source: scholarly_work_events, retraction_status_cache, observed 2026-08-07T06:34:17.273281+00:00
Pith citing papers itemized under the disclosed page cap.
Source: paper_references, paper_reference_links, observed 2026-08-06T15:19:52.549242Z
A source-named dated measurement, never combined with another source.
Source: pith, observed 2026-08-06T15:19:55.807021Z
Reference resolution
0 of 0 outbound references displayed
- verified exact0
- verified fuzzy0
- unresolved0
- parse uncertain0
- malformed identifier0
- metadata mismatch0
External citation measurements
No source-named external measurement is stored.
Outbound references
No outbound reference observations are available for this paper version.
Pith citing papers
Observation 10c52c32-caab-4bfe-a8f0-524dfcfd82ca · inbound
RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs cites this paper.
RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework
Reference 8
- Resolution
- verified exact
- local_arxiv, observed 2026-08-06T15:19:55.859908Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.