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Towards Generalized On-Chip Communication for Programmable Accelerators in Heterogeneous Architectures

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arxiv 2407.04182 v1 pith:MGPZ7PSK submitted 2024-07-04 cs.AR

Towards Generalized On-Chip Communication for Programmable Accelerators in Heterogeneous Architectures

classification cs.AR
keywords acceleratorscommunicationenhancementsacceleratorflexibleheterogeneousincludeon-chip
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved
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We present several enhancements to the open-source ESP platform to support flexible and efficient on-chip communication for programmable accelerators in heterogeneous SoCs. These enhancements include 1) a flexible point-to-point communication mechanism between accelerators, 2) a multicast NoC that supports data forwarding to multiple accelerators simultaneously, 3) accelerator synchronization leveraging the SoC's coherence protocol, 4) an accelerator interface that offers fine-grained control over the communication mode used, and 5) an example ISA extension to support our enhancements. Our solution adds negligible area to the SoC architecture and requires minimal changes to the accelerators themselves. We have validated most of these features in complex FPGA prototypes and plan to include them in the open-source release of ESP in the coming months.

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