Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links
Paper Citation Record · LEDGER
AICircuit: A Multi-Level Dataset and Benchmark for AI-Driven Analog Integrated Circuit Design
As of 10 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 3 inbound Pith citation observations for arXiv:2407.18272.
A citation records a reference. It does not transfer a finding from one paper to another.
Coverage vector
One-hop event checks from named stored sources.
Source: scholarly_work_events, retraction_status_cache, observed 2026-08-10T06:31:04.303077+00:00
Pith citing papers itemized under the disclosed page cap.
Source: paper_references, paper_reference_links, observed 2026-08-07T23:14:10.485794Z
A source-named dated measurement, never combined with another source.
Source: pith, observed 2026-08-07T23:14:10.593552Z
Reference resolution
0 of 0 outbound references displayed
- verified exact0
- verified fuzzy0
- unresolved0
- parse uncertain0
- malformed identifier0
- metadata mismatch0
External citation measurements
No source-named external measurement is stored.
Outbound references
No outbound reference observations are available for this paper version.
Pith citing papers
Observation a4c2df60-ce6f-458e-8224-78bf0884c093 · inbound
DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretraining cites this paper.
DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretraining AICircuit: A Multi-Level Dataset and Benchmark for AI-Driven Analog Integrated Circuit Design
Reference 71
- Resolution
- verified exact
- local_arxiv, observed 2026-08-07T23:14:10.601142Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.
Observation 859e8ef6-01e4-4fb9-bae5-d4e82717b440 · inbound
SABLE: An NDA-Safe Closed-Loop LLM Framework for Analog Circuit Optimization in Industrial EDA Flows cites this paper.
SABLE: An NDA-Safe Closed-Loop LLM Framework for Analog Circuit Optimization in Industrial EDA Flows AICircuit: A Multi-Level Dataset and Benchmark for AI-Driven Analog Integrated Circuit Design
Reference 13
- Resolution
- unresolved
- no resolver link, observed 2026-07-12T00:33:59.659330Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 6d98ba00-5e2d-446f-9108-2385927e5376 · inbound
EXPLORE: Exploration with Guided Search for Analog Topology Generation using Language Models cites this paper.
EXPLORE: Exploration with Guided Search for Analog Topology Generation using Language Models AICircuit: A Multi-Level Dataset and Benchmark for AI-Driven Analog Integrated Circuit Design
Reference 17
- Resolution
- unresolved
- no resolver link, observed 2026-08-02T05:22:44.203481Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.