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REVIEW 4 major objections 5 minor 77 references

DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretraining

T0 review · 4 major / 5 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read The paper claims that self-supervised contrastive pretraining on device-level circuit graphs transfers to graph-level prediction in both analog and digital integrated circuits.

desk verdict A useful first device-level circuit representation with clean held-out evidence on digital delay prediction, but the headline analog results are confounded by pretraining overlap. read the letter →

arxiv 2502.08949 v2 pith:ALGI7PMD submitted 2025-02-13 cs.LG

Sungyoung Lee , Ziyi Wang , Seunggeun Kim , Taekyun Lee , Yao Lai , David Z. Pan This is my paper · ORCID
classification cs.LG
keywords graphcontrastivelearningdevice-levelcircuitgraphsanalogpredictiondigitalneuralnetworkpretrainingdataaugmentationgraph-levelintegratedrepresentation
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper aims to establish that device-level integrated circuits—graphs whose nodes are transistors, resistors, capacitors, current sources, and voltage nets—can be pretrained without any simulation labels, and that the resulting encoder transfers to downstream graph-level prediction tasks. It introduces DICE, described as the first self-supervised graph representation learning framework for both analog and digital circuits, built on graph contrastive learning. The central idea is a pair of circuit-aware augmentations: adding an identical device in series or parallel yields a 'positive' variant that preserves graph-level function, while replacing a subgraph with one that inverts its impedance, energy, or switching behavior yields a 'negative' variant that perturbs it. On three benchmark tasks spanning circuit similarity, digital delay prediction, and analog op-amp metrics, the DICE-initialized encoder outperforms unpretrained and supervised-pretrained baselines. If the claim holds, circuit data scarcity becomes less of a bottleneck because useful training signal is generated from topology alone.

What carries the argument

The load-bearing mechanism is the pair of augmentation rules together with a three-way contrastive objective. Positive augmentation picks a random device and adds an identical device in parallel or series; the paper justifies the preservation of graph-level function by the circuit-theoretic fact that series and parallel combinations consolidate into a single equivalent device, so the augmented graph corresponds to a change in effective device parameters rather than a change in topology-level function. Negative augmentation replaces a device subgraph with one whose impedance, energy, or switching behavior is inverted, producing a new topology with distinct graph-level functionality. The pretrained model is a two-layer Graph Isomorphism Network with edge feature updates, pretrained by maximizing cosine similarity only between positive pairs and minimizing it only between non-equal pairs; negative pairs are not pushed apart directly because they remain localized structural variations of the same circuit. After pretraining, the frozen DICE encoder is placed in parallel with a trainable GNN, followed by a series GNN and a decoder that injects device parameters, and this whole encoder-decoder is fine-tuned for each downstream task.

What would settle it

Run a SPICE simulation on a sample of circuits before and after positive augmentation: take a real amplifier or delay line, add an identical transistor, resistor, or capacitor in series or parallel with a randomly chosen device, sweep the original device parameter values over the ranges used in the downstream tasks, and check whether DC operating point, gain, bandwidth, or delay stay within a small tolerance. If a substantial fraction of positive pairs show large functional changes, the contrastive labels are unreliable; if the encoder still improves downstream performance, the pretraining must be benefiting from some weaker signal than the claimed semantic preservation.

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Extended reading notes

Core claim

The central discovery claimed is that self-supervised contrastive pretraining on device-level circuit graphs produces graph-level representations that transfer well to both analog and digital prediction tasks, and that the pretraining signal can be generated simulation-free by exploiting circuit-specific augmentation semantics. The paper reports that the encoder initialized with DICE outperforms all baselines on every downstream task: circuit similarity prediction reaches 93.94% accuracy versus 91.42% for the best baseline; digital delay prediction reaches an R2 of 0.9468 for rise delay and 0.8085 for fall delay; and analog op-amp metric prediction reaches R2 values of 0.9916 for power, 0.9950 for offset, 0.9374 for CMRR, 0.9769 for gain, and 0.8809 for PSRR. The paper also claims that contrastive pretraining outperforms supervised DC-voltage pretraining and that the benefit persists across several GNN architectures, not just the GIN backbone used for DICE.

Load-bearing premise

The load-bearing premise is that adding an identical device in series or parallel really does leave the circuit's graph-level function unchanged, even though device parameters are ignored in pretraining; if that equivalence fails for realistic circuits or parameter values, the positive-pair labels teach the encoder the wrong thing.

Editorial extensions

If this is right

  • A single pretrained encoder can serve multiple circuit topologies within one task, removing the need for a separate trained model per topology.
  • Pretraining requires no simulator or logic-synthesis tool, so the bottleneck of labeled and even unlabeled circuit data is reduced by generating views from topology alone.
  • Because the same device-level representation covers analog and digital circuits, one initialization can be shared across tasks in both domains.
  • The gains are not locked to one GNN architecture: pretraining with the same loss improves GCN, GraphSAGE, GAT, and GIN encoders in the reported ablations.
  • On the strongest analog task, the paper reports an average improvement over ParaGraph of 15.19% and over DeepGenu of 44.24%, suggesting the pretraining signal is particularly valuable where simulation data are scarce.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A natural extension is to treat logic gates as device-level nodes as well, testing whether a unified device-plus-gate vocabulary improves scalability to large digital blocks; the paper lists this as future work.
  • The series/parallel equivalence underlying positive augmentation is local and parameter-free; in circuits with feedback, cross-coupled pairs, or nonlinear biasing, the equivalence may fail, so a simulation-based guard could be added to filter low-quality positive pairs.
  • The contrastive embeddings could be evaluated as a surrogate for SPICE in sizing or topology search, where the encoder would replace expensive simulation in the optimization loop.
  • If the semantic-preservation assumption is violated, the practical fix would be to weight or re-label positive pairs by measured functional similarity, keeping the framework useful even with noisy augmentation.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. The paper presents DICE, a two-layer GIN pretrained with a graph-contrastive objective on device-level circuit graphs. The pretraining uses two proposed simulation-free augmentations: a 'positive' augmentation that adds an identical device in series or parallel, and a 'negative' augmentation that replaces a device subgraph to change functionality. The pretrained encoder is then frozen and combined with a trainable GNN and decoder for three graph-level downstream tasks: circuit similarity prediction, delay prediction on five delay lines, and prediction of five op-amp performance metrics. The paper reports that DICE outperforms ParaGraph, DeepGenu, and DeepGenp across all three tasks, and includes ablations over pretraining losses, GNN architectures, and encoder depth configurations.

Significance. If the transfer claims hold, DICE would be a useful first step toward self-supervised, device-level representation learning that spans analog and digital circuits, with a multi-topology benchmark and an open-source implementation as auxiliary contributions. The paper is careful to evaluate on separate labeled downstream tasks, so the reported numbers are not circularly fitted. The ablation set is broad, and Task 2 uses delay-line topologies that are not in the pretraining set. However, the empirical case is weakened by the disclosed overlap between Task 3 topologies and the pretraining set, by the absence of uncertainty measures in the headline tables, and by the purely topological justification of the augmentation semantics. These issues can likely be addressed with additional experiments and reporting, so the central idea remains defensible.

major comments (4)
  1. [Section 4.2 and Appendix D.2.3, Tables 2-4] Task 3 is not a held-out-topology transfer test: Appendix D.2.3 explicitly states that the five op-amp topologies used in Task 3 are included in the pretraining dataset, and only the simulation labels are newly generated. Since the frozen DICE encoder has already seen the exact graph structures, the Task 3 margins cited in Section 5 (15.19% average improvement over ParaGraph and 44.24% over DeepGenu) conflate adaptation to seen topologies with transferable analog-circuit representation learning. The overlap is disclosed, but its effect is not quantified and no variant with Task 3 topologies excluded from pretraining is reported; such a held-out analog transfer experiment is needed to support the strongest empirical claim.
  2. [Section 3.2 and Appendix B.1] The semantic validity of the positive augmentation is load-bearing but is supported only by the two-resistor consolidation argument in Appendix B.1. Adding an identical device in series or parallel changes the effective device value and therefore the circuit's electrical behavior, so 'functionally equivalent to altering the parameters' describes an invariance to parameter values rather than preservation of graph-level functionality. The assertion that device parameters do not affect structural circuit properties does not address the fact that all downstream tasks predict parameter-dependent simulation metrics. I request an empirical validation, for example by simulating a sample of original and positively augmented circuits and comparing the predicted Task 2 or Task 3 metrics, and a similar check that negative augmentation reliably perturbs those metrics. Without this, the contrastive labels rest on an unverified semantic assumption.
  3. [Tables 2-4] The head-line results are reported only as averages over three random seeds, with no standard deviations or significance tests. Some of the claimed improvements are small relative to likely seed noise: in Table 3, DICE over LSimSiam is +0.0041 on Rise Delay and +0.0041 on Fall Delay, and the Task 3 metrics differ by about 0.0005 to 0.0009; in Table 2, the difference between DICE and ParaGraph on Rise Delay is +0.0213. Figure 6 shows mu +/- sigma during training, but the final tables omit the corresponding uncertainties. To support the statement that DICE 'consistently outperforms' all baselines, the paper should report standard deviations or confidence intervals for the final metrics.
  4. [Section 4.2 and Appendix D.3] The comparison to DeepGenp is made against a modified version of the pretraining scheme in [40,47]: Appendix D.3 trains a single GNN on seven topologies, whereas the original method trained separate GNNs for each topology. This is a reasonable adaptation for a multi-topology benchmark, but the paper does not state how this change affects the comparison, and the conclusion in Section 5 that DICE outperforms supervised pretraining is presented as a comparison to prior work. Reporting the original per-topology DeepGenp results as an additional baseline, or at least justifying the modification quantitatively, would strengthen the claim.
minor comments (5)
  1. [Section 3.3 and Eq. (3)] The notation around Eq. (3) is inconsistent: the text uses both N^+ and N_+, and the sets X_+(x) and X_neq(x) are not defined with formal set-builder notation. Please unify the notation and define all symbols in one place.
  2. [Section 5] The statement that the results 'follow the conclusion in [34], arguing that similarity minimization is not necessary in contrastive learning' misattributes that conclusion; [34] (SimCLR) uses in-batch negatives, while the no-negative result is from SimSiam [35]. The sentence should be reworded or the citation corrected.
  3. [Table 1] The column header 'DICEGNN' appears to be a formatting artifact, and the row labels 'Pretrained GNN with LSimSiam' and 'Pretrained GNN with LNT-Xent' are ambiguous because every row except the one labeled 'Initial' is produced by a pretrained GNN. Please simplify the labels.
  4. [Appendix D.2.1] The text says the Task 1 training dataset consists of 50 circuits including the 40 pretraining topologies, and the test set contains 5 additional circuits, for a total of 55. Since the pretraining dataset already contains 55 topologies, please clarify whether the remaining 10 pretraining topologies are in the Task 1 training set, are held out, or are unused.
  5. [Appendix C.4] Eq. (9) writes alpha_{u->v} = softmax_{u in N(v)}(h_u . h_v); the softmax is over the neighbor index for a fixed v, but the notation is nonstandard and could be read as a softmax over the whole graph. Please write the normalization explicitly.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: pretraining is unsupervised, downstream labels are newly simulated, and the reported gains are not forced by construction.

full rationale

Walked the derivation chain. The pretraining stage (Sections 3.2-3.3) defines positive, negative, and non-equal relations from augmentation provenance, and the contrastive loss (Eq. 3) is optimized against these self-generated relations; this is a legitimate unsupervised objective, not a disguised prediction. The downstream tasks (Appendix D.2) use separately generated simulation labels, and no pretraining parameter is fitted to those labels. The DICE encoder is frozen during downstream training, so the reported Task 1 accuracy and Task 2/3 R2 values are not forced by the pretraining objective. The self-citations present in the paper ([32], [43], [31]) are benchmark-context and related-work citations; none carries the load of a central claim. The positive-augmentation equivalence argument in Appendix B.1 is an electrical-engineering assumption with independent content; even if debatable, it is not equivalent by construction to downstream simulation outputs. Appendix D.2.3 discloses that Task 3 topologies are included in the pretraining set; this is a benchmark confound and an unquantified overlap that a reader should weigh when interpreting Task 3 margins, but it is not circularity because pretraining did not see the Task 3 simulation labels and the downstream decoder must still fit those labels from the frozen encoder. No step in the paper reduces, by definition, by fitted-input renaming, or by self-citation, to its own inputs. Therefore, no significant circularity is found.

Assumptions & free parameters 3 free parameters · 4 assumptions · 0 invented entities

The pretraining signal and the graph representation rest on domain assumptions about what makes two circuit graphs semantically related. The paper provides heuristic justifications (series/parallel consolidation, impedance inversion) but does not empirically validate that positive augmentations always preserve or negative augmentations always perturb electrical functionality. The temperature coefficients and augmentation counts are chosen hyperparameters with no sensitivity analysis.

free parameters (3)
  • temperature coefficients (tau, tau_p, tau_n) = (0.05, 0.2, 0.05)
    Chosen hyperparameters in the DICE contrastive loss (Eq. 3); no sensitivity analysis reported; results may depend on these values.
  • augmentation counts per topology = 4000 (2000 positive, 2000 negative)
    Pretraining dataset size per topology, chosen by hand; no study of how performance varies with augmentation count.
  • GNN depth configuration (dD, dp, ds) = (2, 0, 2)
    Encoder depth configuration for downstream tasks, selected for the final model; other depths tested in ablation (3) show varying results.
assumptions (4)
  • domain assumption Positive augmentation (adding an identical device in parallel or series) preserves graph-level functionality
    Section 3.2 and Appendix B.1 justify it by series/parallel consolidation of resistors, but this changes device parameter values and only holds if device parameters are ignored in the graph; no simulation check.
  • domain assumption Negative augmentation perturbs graph-level functionality
    Appendix B.2 describes inverting impedance, energy dissipation, or switching behavior; no simulation validation that functionality actually changes as intended.
  • domain assumption Device parameters do not affect structural circuit properties
    Stated in Appendix B.1; central to treating positive augmentations as equivalent, but electrical behavior depends on parameters, so the assumption is only about graph topology.
  • domain assumption The proposed graph construction (9 node types, 5 edge types) captures enough information for downstream tasks
    Section 3.1 defines the mapping; no ablation comparing graph construction variants (acknowledged as future work in Appendix E).

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Cite this review

Pith. "Pith review of DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretraining." pith.science (2026). https://pith.science/paper/ALGI7PMD

@misc{pith2026250208949,
  author       = {Pith},
  title        = {Pith review of: DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretraining},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/ALGI7PMD}},
  note         = {Machine review of arXiv:2502.08949}
}
read the original abstract

Pretraining models with unsupervised graph representation learning has led to significant advancements in domains such as social network analysis, molecular design, and electronic design automation (EDA). However, prior work in EDA has mainly focused on pretraining models for digital circuits, overlooking analog and mixed-signal circuits. To bridge this gap, we introduce DICE, a Device-level Integrated Circuits Encoder, which is the first graph neural network (GNN) pretrained via self-supervised learning specifically tailored for graph-level prediction tasks in both analog and digital circuits. DICE adopts a simulation-free pretraining approach based on graph contrastive learning, leveraging two novel graph augmentation techniques. Experimental results demonstrate substantial performance improvements across three downstream tasks, highlighting the effectiveness of DICE for both analog and digital circuits. The code is available at github.com/brianlsy98/DICE.

Figures

Figures reproduced from arXiv: 2502.08949 by the authors.

Figure 1
Figure 1. Key challenges for graph contrastive learning on device-level circuits. (a) Simple graph augmentations, such as randomly adding edges, can break circuit semantics and result in non-equivalent circuits. (b) Existing approaches require training separate models for each circuit topology, limiting the ability to generalize across diverse structures. device level offers a more foundational approach to pretraining models … view at source ↗
Figure 2
Figure 2. Overview of our graph contrastive learning framework for pretraining DICE. We maximize the cosine similarity between circuits that are in positive relation and minimize it between circuits with a non-equal relation. A detailed explanation of these relations is provided in Section 3.3. 3.1 Graph Construction Considering prior work stated in Appendix A.3, we propose a new method converting device-level circuit into gr… view at source ↗
Figure 3
Figure 3. Rules (a) and examples (b) for positive and negative data augmentation. Positive augmentation adds an identical device in parallel or series, preserving the overall circuit function. Negative augmentation replaces a subgraph, resulting in a circuit with different overall functionality. 3.2 Positive and Negative Data Augmentation To address the limitations of including device parameters in the pretraining dataset (se… view at source ↗
Figures from the paper (6 more)
Figure 4
Figure 4. Figure 4: Encoder (a)–Decoder (b) model architecture used for solving downstream tasks. For Parallel GNN 2 and Series GNN, both node and edge features are updated according to Eqs. (4)–(6). The encoder ( [PITH_FULL_IMAGE:figures/full_fig_p006_4.png]
Figure 5
Figure 5. Figure 5: t-SNE visualization of graph-level features. Each plot represents: (a) initial embeddings, embeddings processed by an (b) untrained GNN, (c) GNN pretrained with LSimSiam, (d) GNN pretrained with LNT-Xent, and (e) GNN pretrained with LDICE (DICE). 4.1 Pretraining Setup.…
Figure 6
Figure 6. Figure 6: Performance curves during downstream task training. Each plot shows the µ ± σ range across 3 different seeds. We compared our method (red), ParaGraph (blue), DeepGenu (green), and DeepGenp (black). Applying DICE leads to stable training, and consistently outperforms al…
Figure 7
Figure 7. Figure 7: Equivalent subgraphs generated through positive data augmentation. Different subgraph [PITH_FULL_IMAGE:figures/full_fig_p016_7.png]
Figure 8
Figure 8. Figure 8: Conversion of characteristics through negative data augmentation. [PITH_FULL_IMAGE:figures/full_fig_p017_8.png]
Figure 9
Figure 9. Figure 9: Masking operation. ⊙ indicates the hadamard product (element-wise multiplication). Masking is our key source of rapid pretraining, with the cost of GPU memory. Algorithm. 1 provides the pseudocode and [PITH_FULL_IMAGE:figures/full_fig_p020_9.png]

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Pith tools

Reviewed August 7, 2026 · model on record in the stance chip above.