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Paper Citation Record · LEDGER

Evaluating Large Language Models for Automatic Register Transfer Logic Generation via High-Level Synthesis

As of 7 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 3 inbound Pith citation observations for arXiv:2408.02793.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2408.02793 v1

Coverage vector

measured 0 of 0 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links

measured 3 of 3 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-07T06:34:17.273281+00:00

measured 3 of 3 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-07T05:27:36.151403Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-05-14T20:32:57.095809Z

Reference resolution

0 of 0 outbound references displayed

  • verified exact0
  • verified fuzzy0
  • unresolved0
  • parse uncertain0
  • malformed identifier0
  • metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

No outbound reference observations are available for this paper version.

Pith citing papers

Observation 04278365-2610-4d17-b8bd-c3e561e715ff · inbound

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols cites this paper.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols Evaluating Large Language Models for Automatic Register Transfer Logic Generation via High-Level Synthesis

Reference 32

Resolution
unresolved
no resolver link, observed 2026-08-07T05:27:36.151403Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-07T05:27:36.151403Z digest=sha256:0eb95479ed8faaa5b72d3bbf45ef6a2c5036bf46a569995e6ee08f29f9e51590

Observation 0ce3fab5-8d44-4723-98fa-6967ca215c9b · inbound

Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems cites this paper.

Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems Evaluating Large Language Models for Automatic Register Transfer Logic Generation via High-Level Synthesis

Reference 23

Resolution
unresolved
no resolver link, observed 2026-08-07T00:31:00.553945Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-07T00:31:00.553945Z digest=sha256:9c2026007bc0d7c9a9217d2294bb00a1fc2000c9e533744429ebfc659fc2e26e

Observation 6bc92dcf-36b7-4490-ba7f-addce36672a4 · inbound

HLS-Seek: QoR-Aware Code Generation for High-Level Synthesis via Proxy Comparative Reward Reinforcement Learning cites this paper.

HLS-Seek: QoR-Aware Code Generation for High-Level Synthesis via Proxy Comparative Reward Reinforcement Learning Evaluating Large Language Models for Automatic Register Transfer Logic Generation via High-Level Synthesis

Reference 24

Resolution
verified exact
arxiv_id, observed 2026-05-14T20:32:57.098956Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

source=pdf_text observed=2026-05-14T20:31:33.331498Z digest=sha256:83328e474a3c841a314ee12aab2d4e1a6f0dfd9b5d0e493cba9b6e2372db5039