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arxiv: 2408.05857 · v1 · submitted 2024-08-11 · 💻 cs.ET · cs.LG

Comparative Evaluation of Memory Technologies for Synaptic Crossbar Arrays- Part 2: Design Knobs and DNN Accuracy Trends

Jeffry Victor , Chunguang Wang , Sumeet K. Gupta This is my paper

Pith reviewed 2026-05-23 22:15 UTC · model grok-4.3

classification 💻 cs.ET cs.LG
keywords synaptic crossbar arraysmemory technologiesDNN accuracyFeFETReRAMin-memory computinghardware non-idealitiesdesign knobs
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The pith

FeFET is best suited for large synaptic crossbar arrays due to its small layout height and high state distinguishability, with ReRAM matching it on higher bit-slices and complex datasets.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper compares the impact of design choices like array size and bit-slice on DNN accuracy for four memory technologies in crossbar arrays. It evaluates how partial wordline activation and custom ADC levels mitigate non-idealities at the 7nm node. FeFET emerges as preferable for large arrays, while ReRAM performs similarly under more challenging conditions. Accuracy improvements reach over 30 percent with the proposed circuit techniques.

Core claim

Compared to the other technologies, FeFET, by virtue of its small layout height and high distinguishability of its memory states, is best suited for large arrays. For higher bit-slices and a more complex dataset (ResNet-50 with Cifar-100) we found that ReRAM matches the performance of FeFET. PWA increases accuracy by up to 32.56% while custom ADC reference levels yield up to 31.62% accuracy enhancement.

What carries the argument

Evaluation of array size, bit-slice number, partial wordline activation (PWA), and custom ADC reference levels on 8T SRAM, FeFET, ReRAM, and SOT-MRAM crossbars for DNN inference accuracy.

If this is right

  • FeFET is preferred for large arrays over SRAM, ReRAM, and SOT-MRAM.
  • ReRAM matches FeFET performance at higher bit-slices with ResNet-50 on CIFAR-100.
  • PWA can improve accuracy by up to 32.56%.
  • Custom ADC reference levels can improve accuracy by up to 31.62%.
  • The technologies respond differently to these accuracy-enhancing techniques.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Designers of in-memory computing hardware may favor FeFET when scaling array sizes.
  • Testing these findings on additional DNN models could confirm the trends.
  • The results highlight the importance of co-optimizing circuit solutions with memory technology choice.
  • Future work might explore power or latency implications of these choices.

Load-bearing premise

The device compact models and circuit simulations at the 7 nm node accurately capture all relevant hardware non-idealities and their quantitative impact on end-to-end DNN inference accuracy.

What would settle it

Fabrication and measurement of 7nm crossbar arrays with these technologies showing reversed accuracy rankings or no benefit from PWA would disprove the claims.

read the original abstract

Crossbar memory arrays have been touted as the workhorse of in-memory computing (IMC)-based acceleration of Deep Neural Networks (DNNs), but the associated hardware non-idealities limit their efficacy. To address this, cross-layer design solutions that reduce the impact of hardware non-idealities on DNN accuracy are needed. In Part 1 of this paper, we established the co-optimization strategies for various memory technologies and their crossbar arrays, and conducted a comparative technology evaluation in the context of IMC robustness. In this part, we analyze various design knobs such as array size and bit-slice (number of bits per device) and their impact on the performance of 8T SRAM, ferroelectric transistor (FeFET), Resistive RAM (ReRAM) and spin-orbit-torque magnetic RAM (SOT-MRAM) in the context of inference accuracy at 7nm technology node. Further, we study the effect of circuit design solutions such as Partial Wordline Activation (PWA) and custom ADC reference levels that reduce the hardware non-idealities and comparatively analyze the response of each technology to such accuracy enhancing techniques. Our results on ResNet-20 (with CIFAR-10) show that PWA increases accuracy by up to 32.56% while custom ADC reference levels yield up to 31.62% accuracy enhancement. We observe that compared to the other technologies, FeFET, by virtue of its small layout height and high distinguishability of its memory states, is best suited for large arrays. For higher bit-slices and a more complex dataset (ResNet-50 with Cifar-100) we found that ReRAM matches the performance of FeFET.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript compares the performance of 8T SRAM, FeFET, ReRAM, and SOT-MRAM in synaptic crossbar arrays for DNN inference at the 7 nm technology node. It examines the influence of design parameters including array size and bit-slice on accuracy, as well as the benefits of Partial Wordline Activation (PWA) and custom ADC reference levels. Key findings include accuracy improvements of up to 32.56% with PWA and 31.62% with custom ADCs on ResNet-20/CIFAR-10, with FeFET identified as optimal for large arrays and ReRAM performing comparably at higher bit-slices on ResNet-50/CIFAR-100.

Significance. Should the compact models and simulations prove accurate, this work contributes comparative data on memory technologies for in-memory computing, highlighting effective design strategies to mitigate hardware non-idealities. It extends prior work in Part 1 by focusing on accuracy trends and circuit-level solutions.

major comments (2)
  1. [Abstract] Abstract: The reported accuracy deltas (32.56% from PWA, 31.62% from custom ADCs) and technology rankings (FeFET superiority for large arrays, ReRAM parity at higher bit-slices) rest entirely on 7 nm SPICE simulations; no error bars, sensitivity analysis to model parameters, or silicon validation of the compact models is referenced, directly affecting the load-bearing quantitative claims.
  2. [Device modeling and simulation methodology] Device modeling and simulation methodology sections: The central assumption that the chosen compact models quantitatively reproduce all dominant non-idealities (device variability, IR drop, ADC quantization, sense-amplifier offset) and that their aggregate effect on end-to-end DNN accuracy is faithfully captured lacks any cross-check against measured array data or ablation on model fidelity; any systematic mismatch would scale the reported deltas and rankings.
minor comments (2)
  1. [Abstract] Abstract: Reference to 'Part 1' lacks a citation or brief summary of its co-optimization strategies, reducing standalone readability.
  2. [Results] Results presentation: Tables and figures reporting accuracy trends should specify the number of Monte Carlo runs or variability sources considered to allow assessment of statistical significance.

Simulated Author's Rebuttal

2 responses · 1 unresolved

We thank the referee for the constructive comments. Below we respond point-by-point to the major comments. This work is a simulation study at the 7 nm node; we address the implications of that scope honestly.

read point-by-point responses

  1. Referee: [Abstract] Abstract: The reported accuracy deltas (32.56% from PWA, 31.62% from custom ADCs) and technology rankings (FeFET superiority for large arrays, ReRAM parity at higher bit-slices) rest entirely on 7 nm SPICE simulations; no error bars, sensitivity analysis to model parameters, or silicon validation of the compact models is referenced, directly affecting the load-bearing quantitative claims.

    Authors: We agree that the quantitative deltas and rankings are obtained exclusively from the described 7 nm SPICE simulations. The manuscript will be revised to state explicitly in the abstract that all reported accuracy numbers and technology comparisons are simulation results. No error bars or parameter sensitivity sweeps were performed; adding them would require a substantial additional study that is outside the present scope. Silicon validation data for a consistent cross-technology comparison at 7 nm is not available to us. revision: partial

  2. Referee: [Device modeling and simulation methodology] Device modeling and simulation methodology sections: The central assumption that the chosen compact models quantitatively reproduce all dominant non-idealities (device variability, IR drop, ADC quantization, sense-amplifier offset) and that their aggregate effect on end-to-end DNN accuracy is faithfully captured lacks any cross-check against measured array data or ablation on model fidelity; any systematic mismatch would scale the reported deltas and rankings.

    Authors: The methodology section specifies the compact models employed and the non-idealities that are included. We do not possess measured array-level data that could serve as an independent cross-check for all four technologies. We can add a short paragraph in the revised manuscript discussing the reliance on published compact-model fidelity and the consequent limitations on absolute accuracy predictions, while preserving the relative trends that are the paper's focus. revision: partial

standing simulated objections not resolved
  • Silicon validation or measured array data against which to cross-check the compact models and the aggregate impact of all modeled non-idealities

Circularity Check

0 steps flagged

No circularity: results are direct simulation outputs

full rationale

The paper reports DNN inference accuracy trends obtained from circuit simulations of crossbar arrays using compact models for 8T SRAM, FeFET, ReRAM and SOT-MRAM at the 7 nm node. Accuracy deltas (e.g., PWA up to 32.56 %, custom ADC up to 31.62 %) and technology rankings are stated as outputs of these end-to-end simulations under varying array sizes and bit-slices. No equations, fitted parameters, or self-referential definitions are present that would reduce any reported prediction to its own inputs by construction. The single reference to 'Part 1' concerns prior co-optimization strategies and is not load-bearing for the accuracy numbers or rankings presented here. The derivation chain therefore consists of independent simulation runs rather than any of the enumerated circular patterns.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Abstract-only review; no explicit free parameters, axioms, or invented entities are stated. Simulations presumably rely on standard compact models for each memory technology whose parameters are taken from prior device literature.

pith-pipeline@v0.9.0 · 5851 in / 1219 out tokens · 23268 ms · 2026-05-23T22:15:34.433956+00:00 · methodology

discussion (0)

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