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Deep Circuit Compression for Quantum Dynamics via Tensor Networks

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arxiv 2409.16361 v2 pith:NRRKS663 submitted 2024-09-24 quant-ph

classification quant-ph
keywords circuitdepthquantumcircuitsalgorithmdepthsfactorsimulation
verification ladder T0 review T1 audit T2 compute T3 formal
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abstract

Dynamic quantum simulation is a leading application for achieving quantum advantage. However, high circuit depths remain a limiting factor on near-term quantum hardware. We present a compilation algorithm based on Matrix Product Operators for generating compressed circuits enabling real-time simulation on digital quantum computers, that for a given depth are more accurate than all Trotterizations of the same depth. By the efficient use of environment tensors, the algorithm is scalable in depth beyond prior work, and we present circuit compilations of up to 64 layers of $SU(4)$ gates. Surpassing only 1D circuits, our approach can flexibly target a particular quasi-2D gate topology. We demonstrate this by compiling a 52-qubit 2D Transverse-Field Ising propagator onto the IBM Heavy-Hex topology. For all circuit depths and widths tested, we produce circuits with smaller errors than all equivalent depth Trotter unitaries, corresponding to reductions in error by up to 4 orders of magnitude and circuit depth compressions with a factor of over 6.

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Cited by 3 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Learning Circuits with Infinite Tensor Networks

    quant-ph 2025-06 conditional novelty 7.0 of 10

    Infinite tensor networks are used to compile translation-invariant quantum circuits that prepare ground states and time evolution operators with fewer gates than Trotterization.

  2. Observation of hadron scattering in a lattice gauge theory on a quantum computer

    quant-ph 2025-05 conditional novelty 6.0 of 10

    The authors observe elastic and confined scattering, plus mass-quench-induced inelastic dynamics, in a 1+1D U(1) lattice gauge theory on IBM quantum hardware.

  3. High-Performance Contraction of Quantum Circuits for Riemannian Optimization

    quant-ph 2025-06 conditional novelty 5.0 of 10

    A matrix-free, cached Hessian framework enables memory-efficient Riemannian trust-region optimization of quantum circuit gates, with near-linear parallel speedup up to 112 threads.

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