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REVIEW 4 major objections 6 minor 21 references

Timing-driven Approximate Logic Synthesis Based on Double-chase Grey Wolf Optimizer

T0 review · 4 major / 6 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read Approximate logic synthesis gains the most timing when critical-path depth and area are optimized together, and the proposed double-chase grey wolf optimizer with post-sizing reports average critical-path delay reductions of 27.13% at 5%…

desk verdict A genuine algorithmic variant with an honest experimental effort, but the core timing claim is weakened by an objective mismatch and in-sample tuning. read the letter →

arxiv 2411.10990 v1 pith:PAHXMQYY submitted 2024-11-17 cs.AR

Xiangfei Hu , Yuyang Ye , Tinghuan Chen , Hao Yan , Bei Yu This is my paper · ORCID
classification cs.AR
keywords approximatelogicsynthesisgreywolfoptimizercriticalpathdelaygatesizingerrorratenormalizedmeandistancelocalchangestimingoptimization
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper argues that approximate logic synthesis should optimize critical path depth and area simultaneously, because depth-only methods leave area savings on the table and area-only methods rarely shorten the critical path. It introduces a double-chase grey wolf optimizer that explores local approximate changes (replacing wires or setting wires to constants) while tracking both depth and area, then converts the accumulated area reduction into stronger drive-strength gates, cutting delay further. On 28nm benchmarks, the framework claims average critical path delay reductions of 27.13% under a 5% error-rate constraint and 38.54% under a 2.44% normalized-mean-error-distance constraint, exceeding prior depth-driven, area-driven, and single-chase baselines with comparable runtime. If correct, the recipe makes approximation a timing tool rather than just an area or power tool.

What carries the argument

The central object is the double-chase grey wolf optimizer (DCGWO), an extension of the grey wolf optimizer in which the approximate-circuit population is split into a leader, three elite circuits, and an omega group. The leader guides the elites in Chase 1, and the elites guide the omegas in Chase 2; each chase alternates between circuit searching (applying wire-by-wire or wire-by-constant local changes on sampled critical-path gates, choosing replacement gates by output similarity) and circuit reproduction (recombining high-scoring primary-output transitive-fanin pairs from two parents). Fitness combines the critical-path-depth ratio and the area ratio, and a quadratic scheme gradually relaxes the error constraint across iterations. The companion mechanism is post-optimization: deletion of dangling gates followed by area-constrained gate resizing, which converts the accumulated area reduction into reduced critical path delay.

What would settle it

For any benchmark, enumerate all Pareto-front approximate circuits produced by the optimizer before post-optimization, apply the same dangling-gate deletion and gate-resizing step to each, and check whether the circuit selected by the pre-sizing fitness function has the smallest post-sizing critical path delay; a single counterexample where another Pareto candidate is faster after resizing would falsify the claim that the optimizer's choice yields the maximum delay reduction.

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Extended reading notes

Core claim

Existing timing-driven approximate logic synthesis methods pick approximate changes by either critical-path depth or area alone, so they miss the best final timing. The paper's central claim is that the right objective is a weighted combination of critical-path-depth ratio and area ratio during search, and that a hierarchical 'double-chase' grey wolf optimizer can explore this two-objective space more effectively than greedy, genetic, or single-chase methods. The chosen approximate circuit is then passed through post-optimization that deletes dangling gates and resizes remaining gates under an area constraint, turning area saved by approximation into drive-strength enhancement on critical paths. The reported outcome is a maximum average critical path delay reduction (27.13% under an error-rate constraint of 5%, and 38.54% under a normalized-mean-error-distance constraint of 2.44%) at the same error and area constraints as the compared methods.

Load-bearing premise

The circuit that scores best on the pre-sizing depth-and-area fitness function is assumed to remain the best after post-optimization resizing, so the reported final delay actually follows from the optimizer's choice.

Editorial extensions

If this is right

  • Depth and area should be treated as simultaneous objectives during approximate search, since depth-only approximation leaves area savings that could be spent on drive strength, and area-only approximation rarely shortens the critical path.
  • Area reduction created by approximation is a timing resource: after dangling-gate deletion, the saved area can be invested in resizing critical-path gates for lower delay.
  • The hierarchical double-chase population produces smaller final delay ratios than single-chase grey wolf optimization within the same iteration budget.
  • The reported benefit persists across error budgets and area constraints, ranging from 1% to 5% error rate, 0.48% to 2.44% normalized mean error distance, and 0.8x to 1.2x area settings.
  • Runtime stays competitive because the fan-in adjacency representation makes local approximate changes cheap to apply and the population-based search parallelizes.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A testable extension is to make the error-constraint relaxation schedule circuit-adaptive; the fixed quadratic scheme may leave unexplored depth-area pairs on circuits with very different error tolerances.
  • Because final delay comes from drive-strength resizing, the depth/area weight (wd=0.8) should be recalibrated per cell library; on libraries with a different area-to-delay mapping, the same fitness ranking may not maximize post-sizing delay.
  • The fan-in adjacency representation discards wire and parasitic information, so the reported gains are likely best on gate-delay-dominated designs; adding wire-aware delay estimates would test how far the result carries to interconnect-dominated circuits.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 6 minor

Summary. The paper proposes a timing-driven approximate logic synthesis (ALS) framework based on a double-chase grey wolf optimizer (DCGWO). Circuits are stored as fan-in adjacency lists, and LACs (wire-by-wire and wire-by-constant) are applied to reduce critical-path depth and area under ER or NMED error constraints. The optimizer ranks circuits with a weighted depth/area fitness function, and a final post-optimization step removes dangling gates and resizes remaining gates under an area constraint to convert area savings into further delay reduction. Experiments on ISCAS-85 and EPFL benchmarks with TSMC 28nm report average critical-path delay reductions of 27.13% under a 5% ER constraint and 38.54% under a 2.44% NMED constraint, claiming improvements over area-driven, depth-driven, and single-chase GWO baselines.

Significance. If the reported results survive re-evaluation, the work would be a practically useful contribution: the double-chase strategy is a plausible way to balance depth and area objectives in ALS, the adjacency-list representation is simple and efficient, and the post-sizing step is a sensible mechanism for converting area slack into timing. The paper also compares against several established baselines and reports runtime. However, the quantitative claims are not yet fully established because the depth weight is tuned on the evaluation benchmarks, the stochastic optimizer is reported without variance, and the optimizer's search objective is not the same as the headline post-sizing delay metric.

major comments (4)
  1. [IV-A, Fig. 6] The depth weight wd is selected by running the framework on the benchmark circuits used for evaluation and choosing the wd that minimizes the average post-sizing Ratiocpd under the tightest and loosest ER/NMED constraints. This is parameter tuning on the test set, so the headline 27.13% and 38.54% average reductions reported in Tables II and III are not independent estimates. Please fix wd on a validation split or through leave-one-out selection, or report results across a range of wd to show that the main conclusions are robust to this choice.
  2. [Tables II and III, Section III-B] DCGWO is stochastic: the initial population is random, target and switch gates are sampled, and the decision parameters D and W involve random values rc and r1. The tables report a single run per circuit with no variance or number of trials. The claimed margins over HEDALS and the other baselines are therefore not statistically grounded. Please report mean and standard deviation (or a box plot) over at least 10 independent seeds, and include a paired significance test against the main baselines.
  3. [III-B Eq. (8), III-C] The fitness function in Eq. (8) ranks approximate circuits using pre-sizing depth and area ratios, but the reported metric Ratiocpd = CPDfac/CPDori is measured after Design Compiler drive-strength resizing in Section III-C. The paper gives no evidence that the pre-sizing Pareto ordering is preserved after resizing; post-sizing delay depends on fanout, load, and which gates lie on the critical path, information that is largely absent from the fan-in-only representation. Thus the abstract's claim that the framework achieves 'maximum critical path delay reduction' does not follow from the optimizer's selection rule. Please add an ablation that evaluates all Pareto-front candidates with the full post-sizing flow and reports the rank correlation between Eq. (8) fitness and final Ratiocpd, or modify the final selection to use post-sizing CPD directly.
  4. [IV-B, Tables II and III] The 'GWO (single-chase)' baseline is under-specified: the paper does not state which fitness function, which weights, which thresholds, and which stopping criterion this variant uses, nor whether its hyperparameters were tuned in the same way as those of DCGWO. Without this information the comparison is not reproducible and the claimed benefit of the double-chase mechanism cannot be separated from implementation details. Please describe the baseline configuration completely and, ideally, provide the artifact or code for all compared methods.
minor comments (6)
  1. [Abstract] The full text contains a leftover LaTeX comment in the abstract ('%based on double-chase grey wolf optimizer (DCGWO).'), which interrupts the sentence; please clean it up.
  2. [Equation (3)] The weights wt and we are given as numbers (0.9*CPDori, 0.1, 0.2) but the terms 1/Ta and 1/Error have different units and scales; please clarify how these weights are normalized or justified.
  3. [IV-A] The empirical parameter b in the asymptotic error constraint relaxation (Error_iter_cons = b*iter^2 + Error0_cons) is not reported; please give the values used for the ER and NMED experiments.
  4. [Fig. 7] Figure 7 compares only HEDALS and single-chase GWO, not VECBEE-SASIMI or VaACS; please state why those baselines are omitted from the constraint-sweep plots.
  5. [References] Reference [14] contains a typo ('Eurpoe') and reference [18] contains a duplicated journal prefix in 'IEEE IEEE Trans. Evol. Comput.'; please correct these.
  6. [III-B, Eq. (8)] The term 'critical path depth' is used interchangeably with timing information from PrimeTime; please specify whether Depthapp is a logic level count or a static-timing delay value, since the difference matters for interpreting Eq. (8).

Circularity Check

1 steps flagged · score 6.0 of 10

Reported delay reductions are the same metric used to tune wd: the paper chooses wd=0.8 by minimizing average Ratiocpd on the benchmark set and then presents the resulting Ratiocpd as the framework's achievement.

  1. fitted input called prediction [Section IV-A (Parameter Setting), Fig. 6; reported in Section IV-B, Tables II/III]
    "For circuit fitness F it, we determine the optimal weights based on critical path delay ratios of the final approximate circuits over the accurate circuits (i.e., Ratio cpd = CP Df ac / CP Dori ). Fig. 6 illustrates that the minimum Ratio cpd are achieved under both the tightest and loosest error constraints when wd is 0.8 and wa = 1− wd is 0.2. Therefore, we follow this setting. ... our framework maximizes the average critical path delay reduction to 27.13% with shorter runtime under the 5% ER constraint."

    The central reported metric, Ratiocpd, is exactly the quantity used to select the weight wd in the fitness function of Eq. (8). The authors run the full framework on the same benchmarks for different wd values, measure the final post-sizing critical path delay ratio, and pick wd=0.8 because it minimizes that ratio. They then report the resulting Ratiocpd values—converted into the headline 27.13% and 38.54% reductions—as the method's achieved performance. The 'prediction' is therefore not an independent evaluation; it is the value of the tuning objective after selection on the test set. Since the comparison baselines are not given the same test-set tuning, the claimed advantage is partly a selection artifact rather than a derived result.

full rationale

The core ALS flow—fan-in adjacency representation, double-chase GWO search, Pareto sorting, dangling-gate deletion, and Design Compiler post-sizing—is internally defined and is not a restatement of its inputs. The primary circularity is confined to parameter selection: Section IV-A states that the depth/area weight wd is chosen by measuring Ratiocpd = CPDfac/CPDori of the final approximate circuits on the same benchmarks, and Fig. 6 selects wd=0.8 because it gives the minimum Ratiocpd. Section IV-B then reports those same Ratiocpd values (converted to 27.13% and 38.54% reductions) as the method's result. Thus the central quantitative claim is the fitting objective for wd; the reported numbers are partly constructed by the tuning step rather than being out-of-sample predictions. This is a test-set selection artifact and makes the comparison to HEDALS/VaACS/VECBEE-SASIMI unfair, since those baselines are not tuned on the same objective. The paper's other uses of self-citation (e.g., [3]) are background only and not load-bearing. The post-sizing vs pre-sizing fitness mismatch is a separate correctness concern, not a circularity. Overall, partial circularity: one fitted parameter directly controls the headline metric.

Assumptions & free parameters 5 free parameters · 5 assumptions · 0 invented entities

The central claim depends on the listed hyperparameters and domain assumptions; none are derived from first principles and no code is shipped. No new physical entities are postulated; the double-chase is a new algorithm structure, not an invented entity in the ledger sense.

free parameters (5)
  • wd = 0.8
    Depth weight in the fitness function of Eq. (8), selected by sweeping on the same benchmarks to minimize average Ratio_cpd (Section IV-A, Fig. 6).
  • we (Level error weight) = 0.1 (ER), 0.2 (NMED)
    Hand-set weights in the PO-TFI pair evaluation function Level, Eq. (3), Section IV-A.
  • wt (Level timing weight) = 0.9 x CPD_ori
    Hand-set weight in Eq. (3), scaled to the benchmark delay, Section IV-A.
  • b (error relaxation parameter) = not reported
    Quadratic relaxation Error^iter_cons = b*iter^2 + Error^0_cons in Section III-B; b is empirical and its value is not given.
  • Population size N and iteration limit Imax = N=30, Imax=20
    Metaheuristic control parameters from Section IV-A.
assumptions (5)
  • domain assumption Fan-in adjacency lists without explicit wire information suffice to apply and evaluate LACs.
    Section III-A builds the circuit representation solely from gate fan-in relationships, discarding wire information.
  • domain assumption Output similarity between target gate and candidate switch gate or constant is a reliable proxy for the error introduced by a LAC.
    Section III-B selects switch gates based on the percentage of cycles with matching output values, assuming this bounds the true ER/NMED.
  • domain assumption The weighted-sum fitness of delay ratio and area ratio is a suitable proxy for the final post-sizing critical path delay.
    Eq. (8) defines fitness; post-optimization in Section III-C assumes optimizing this proxy maximizes final CPD reduction.
  • standard math Non-dominated sorting and crowding distance (NSGA-II style) preserve population diversity and guide the optimizer to near-global optima.
    Section III-B adopts non-dominated sorting from [18] and crowding distance from [17] without modification.
  • domain assumption Results on ISCAS'85 and EPFL benchmarks under TSMC 28nm are representative of the method's performance on other circuits and technologies.
    Section IV evaluates only these open benchmarks; no cross-technology or cross-library validation is provided.

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Cite this review

Pith. "Pith review of Timing-driven Approximate Logic Synthesis Based on Double-chase Grey Wolf Optimizer." pith.science (2026). https://pith.science/paper/PAHXMQYY

@misc{pith2026241110990,
  author       = {Pith},
  title        = {Pith review of: Timing-driven Approximate Logic Synthesis Based on Double-chase Grey Wolf Optimizer},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/PAHXMQYY}},
  note         = {Machine review of arXiv:2411.10990}
}
read the original abstract

With the shrinking technology nodes, timing optimization becomes increasingly challenging. Approximate logic synthesis (ALS) can perform local approximate changes (LACs) on circuits to optimize timing with the cost of slight inaccuracy. However, existing ALS methods that focus solely on critical path depth reduction (depth-driven methods) or area minimization (area-driven methods) are inefficient in achieving optimal timing improvement. %based on double-chase grey wolf optimizer (DCGWO). where we employ a double-chase grey wolf optimizer to explore and apply LACs, simultaneously bringing excellent critical path shortening and area reduction under error constraints. According to experiments on open-source circuits with TSMC 28nm technology, compared to the SOTA method, our framework can generate approximate circuits with greater critical path delay reduction under different error and area constraints.

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Reference graph

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