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REVIEW 3 major objections 4 minor 31 references

Generalized Ping-Pong: Off-Chip Memory Bandwidth Centric Pipelining Strategy for Processing-In-Memory Accelerators

T0 review · 3 major / 4 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read The paper claims that a staggered 'generalized ping-pong' schedule keeps both PIM macros and off-chip bandwidth near 100% utilized, achieving 1.22–7.71x speedups over naive ping-pong for large DNN workloads.

desk verdict Useful closed-form model for staggered write/compute in PIM, but headline speedups rest on a fractional-macro idealization and Eq. (6) inverts the ratio; still worth a referee. read the letter →

arxiv 2411.13054 v1 pith:N6WXO6SP submitted 2024-11-20 cs.AR

Ruibao Wang , Bonan Yan This is my paper · ORCID
classification cs.AR
keywords processing-in-memorySRAMPIMpipeliningmemorybandwidthconcurrentwrite/computeGeMMaccelerationdeepneuralnetworksping-pongscheduling
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper argues that the two standard ways to interleave weight writes with computation in processing-in-memory (PIM) accelerators—in-situ write/compute and naive ping-pong—leave either the compute macros or the off-chip memory bandwidth idle, because the time to rewrite weights rarely equals the time to compute with them. It proposes 'generalized ping-pong': stagger the start times of the PIM macros so that the number of macros writing at any cycle is exactly the share that keeps the off-chip link continuously busy, while every macro alternates between writing and computing without idle states. The authors claim this schedule gives over 1.67x speedup when the off-chip link is fully available, and 1.22–7.71x speedups versus naive ping-pong when the link is limited to 8–256 bytes per cycle, with near-100% utilization of both macros and bandwidth. This matters because large DNN models no longer fit on-chip, so weights must be streamed in during inference and the bottleneck shifts to off-chip memory bandwidth.

What carries the argument

The load-bearing identity is Eq. (4), nummacro = (timePIM + timerewrite) * band / (timerewrite * s), which turns a ratio of compute time to write time into a concrete number of macros whose staggered write phases exactly fill the off-chip link given each macro's write speed. This is the mechanism that transforms the ping-pong idea from two alternating groups into an arbitrary-depth pipeline: writes are spread across macros rather than synchronized, so the off-chip bandwidth sees a continuous flat demand and no macro ever waits. The runtime adaptation formula Eq. (9) then predicts the performance remaining when bandwidth is reduced by a factor n, and this formula is what yields the reported 7.71x advantage at one 64th of the design bandwidth. The hardware enabler is a generalized execution unit and an assembler/ISA extension that let a PUMA-style PIM core issue the staggered schedule.

What would settle it

Measure, on a real SRAM-PIM test chip with K macros, the achieved execution time for a fixed GeMM batch as the write speed s is swept across the design range, and compare against Eq. (4)'s prediction; if the measured time deviates from the model by more than the rounding error reported in Table II for K ≥ 80 macros, the continuous-stagger claim fails. Alternatively, inject random latency into the off-chip link and observe whether macro idle cycles appear at a rate the model predicts to be zero.

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Extended reading notes

Core claim

The central discovery is a closed-form scheduling law: for a fixed off-chip bandwidth band, macro write speed s, PIM compute time timePIM, and rewrite time timerewrite, the number of macros that can run with neither macro idle time nor bandwidth idle time is nummacro = (timePIM + timerewrite) * band / (timerewrite * s). This law follows from setting the aggregate write demand of staggered macros exactly equal to the available bandwidth and requiring each macro's write/compute cycle to repeat back-to-back. With it, the write:compute ratio of an individual macro, rather than chip-wide synchronization, determines how many macros the accelerator should instantiate or keep active. The paper implements this schedule on a PUMA-based design with 16 cores of 16 macros each and reports that, across write:compute ratios from 8:1 to 1:7, generalized ping-pong either outperforms both baselines or matches the better one while using fewer macros; at ratio 1:7 it achieves 2.51x speedup over naive ping-pong and 5.03x over in-situ, and at ratio 8:1 it uses 43.75% fewer macros than naive ping-pong with equal performance.

Load-bearing premise

The whole speedup rests on the assumption that write and compute times are deterministic and that a macro can be started at any fractional offset, so in practice the integer granularity of real hardware and any jitter in the memory link make the promised 100% utilizations and exact speedups approximate.

Editorial extensions

If this is right

  • In the design phase, Eq. (4) tells an architect how many macros to instantiate for a given off-chip bandwidth and target write:compute ratio, or conversely how much bandwidth is needed for a fixed macro count.
  • For large models whose weights stream from off-chip memory, generalized ping-pong keeps the memory link continuously busy, so PIM throughput scales with available bandwidth instead of stalling on either compute or write phases.
  • When off-chip bandwidth is shared and varies at runtime, the same schedule preserves more performance than either baseline: at one 64th of design bandwidth, the paper reports 5.38x over in-situ and 7.71x over naive ping-pong.
  • At balance (timerewrite = timePIM), generalized ping-pong reduces to naive ping-pong and outperforms in-situ by 2x, so it is a strict generalization rather than a competing alternative.
  • When writes dominate (timerewrite > timePIM), generalized ping-pong matches naive ping-pong in performance while using 43.75% fewer macros at an 8:1 ratio, saving area and power.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Editorial inference: the same staggering law could be applied to heterogeneous macros with different write speeds or to workloads whose write:compute ratio changes per layer, but Eq. (4) would then need to become a dynamic scheduling problem rather than a single closed form.
  • Editorial inference: the continuous-macro assumption means realizable gain on a fixed chip is quantized; Table II shows deviations up to about 10% at low bandwidth, so practical speedups on small macro counts will sit below the ideal curve until rounding becomes negligible.
  • Editorial inference: the bandwidth-centric staggering argument could also apply to other memory-bound accelerators with explicit load and compute phases, such as systolic arrays with on-chip weight staging, not just PIM arrays.
  • Editorial inference: because the schedule relies on deterministic write and compute times, a jittery memory subsystem (for example, DRAM refresh or contention) would require slack; the Verilog-based results assume a clean off-chip link.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 4 minor

Summary. The paper proposes a scheduling strategy called 'generalized ping-pong' for SRAM-based processing-in-memory (PIM) accelerators. Instead of synchronizing all macros (in-situ write/compute) or splitting them into two fixed groups (naive ping-pong), the strategy staggers the start times of each macro's weight-rewrite/compute cycle so that off-chip memory bandwidth demand is spread evenly. The authors derive a continuous-time model for the number of supported macros (Eq. 4), compare execution times and macro counts among the three strategies (Eqs. 5-9), implement the strategy on a PUMA-like Verilog accelerator with a custom assembler, and report speedups of 1.67x or more at full bandwidth and 1.22-7.71x versus naive ping-pong when bandwidth is limited to 8-256 bytes/cycle.

Significance. If the central claims held exactly, the paper would offer a useful bandwidth-centric pipelining principle for PIM accelerators facing weight-reloading pressure from large DNN models. The open-source Verilog implementation, assembler, and quantitative model are concrete contributions that support reproducibility. However, the headline speedups and the 'fully utilizing off-chip bandwidth' claim rest on a continuous-fractional-macro idealization that no finite integer schedule can realize in general, and one of the key formulas (Eq. 6) is dimensionally mislabeled. The core scheduling idea is still plausible and worth pursuing, but the current manuscript overstates the exactness of its quantitative predictions.

major comments (3)
  1. [Section IV.B, Eq. (6)] Eq. (6) labels a ratio as an 'execution time ratio,' but the formula actually gives the ratio of macro counts (or throughput) and is inverted relative to execution time. Let r = nin*s/sizeOU = timePIM/timerewrite. Eq. (6) states generalized:in-situ:naive = (r+1):1:... For r=7 (the 1:7 case in Fig. 6), this says generalized ping-pong takes 8x as long as in-situ, yet Fig. 6(a) reports a 5.03x speedup for generalized ping-pong over in-situ. The correct execution-time ratio is the reciprocal of Eq. (6), e.g., 1:(r+1):... This error affects the central quantitative comparison in Section IV.B and must be corrected.
  2. [Section IV.B, Eq. (4) and Table II] Eq. (4) treats the number of macros as a continuous real number, but a physical accelerator has an integer number of macros whose write bursts are contiguous at the fixed speed s. For a finite integer N, 100% off-chip bandwidth utilization requires N * timerewrite/(timePIM+timerewrite) to be an integer in every cycle. For example, with timerewrite:timePIM = 2:5 and band=s, Eq. (4) gives N=3.5; with N=3 macros the bandwidth is idle 1/7 of the time, and with N=4 macros the demand becomes 8/7 of s, violating the constraint. No periodic schedule of contiguous-burst macros achieves both 100% macro utilization and 100% bandwidth utilization in this case. Table II confirms the systematic shortfall (e.g., 78.08% theory vs 75.00% practice at band=256). The abstract's 'fully utilizing the off-chip memory bandwidth' and the quantitative speedup ranges are therefore upper bounds from a fractional-macro idealization, not exact properties of the discrete system. The manuscript should state this limitation explicitly and verify the headline claims against integer schedules.
  3. [Section V.A, Figs. 6-7] The evaluation does not specify the workloads used to generate Figs. 6 and 7 or Table II. The text only mentions 'large-scale consecutive GeMM operations with BLAS level benchmarks,' but it does not state matrix dimensions, number of layers, batch sizes, or how the write-time/compute-time ratio is varied in the sweeps. Without this information, the reported execution times, macro counts, and bandwidth-reduction curves cannot be reproduced or compared across strategies. Please provide concrete benchmark configurations and, for Fig. 7, the exact design-phase operating point at which bandwidth is reduced.
minor comments (4)
  1. [Abstract and Section III] The phrase 'fully utilizing the off-chip memory bandwidth' appears without qualification; since the model allows fractional macro counts and Table II shows discrepancies, this should be hedged as 'in the continuous model' or 'approximately.'
  2. [Throughout] There are several typos and inconsistent notations, e.g., 'generlized ping-poing' in the abstract, 'arbitanr y' in Section III, 'in' instead of 'nin' in Eq. (5), and '7:52:1' instead of '7.52:1' in Table II.
  3. [Fig. 3(c)] The caption text says 'At most, four macros are simultaneously writing' for generalized ping-pong, but the accompanying example with a 1:3 write:compute ratio and four macros has at most one macro writing at a time; please check whether this is a typo in the figure or caption.
  4. [Section IV.B, Eq. (9)] The derivation of Eq. (9) is not shown; since it is used to claim that generalized ping-pong retains a greater portion of performance under bandwidth reduction, a short derivation or reference to the intermediate steps would improve clarity.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: Eq. (4) sizes the macro count from first-principles timing definitions; the speedup comparisons to baselines follow from the same definitions, and Table II explicitly acknowledges the fractional-macro idealization as a modeling limitation rather than hiding it.

full rationale

The paper's derivation chain begins with first-principles timing definitions: timePIM = sizemacro * nin / sizeOU and timerewrite = sizemacro / s, stated in Section IV.B. Eq. (4) then computes the number of macros supportable under a given off-chip bandwidth by setting nummacro = (timePIM + timerewrite) * band / (timerewrite * s), which is a sizing equation derived from the average per-macro bandwidth demand timerewrite*s/(timePIM + timerewrite). This is not a fitted target; the claimed speedups are not inserted as inputs. The baseline strategies are modeled from the same timing definitions: in situ write/compute consumes full bandwidth only during its synchronized write phases, and naive ping-pong halves average bandwidth demand when macros are idle in alternating groups. Eq. (5) and Eq. (6) are algebraic comparisons of these models, not empirical fits, and the 1.22-7.71x speedup ranges are consequences of those comparisons. The self-citations in the reference list, e.g., [18] and [20], are used as background SRAM-PIM macro and compute-in-memory design references; they do not carry the load-bearing argument, so no self-citation circularity is present. The main caveat, the continuous/fractional macro idealization, is explicitly acknowledged in the paper: Table II and the surrounding text state that the model uses a fractional number of PIM macros while the Verilog implementation uses an integer number, producing discrepancies such as 78.08% theory versus 75.00% practice at band = 256. This is an accuracy and idealization caveat about the granularity of the staggered schedule, not a circular definition or a fitted-parameter-renamed-as-prediction. The work is also self-contained and reproducible via the open-sourced Verilog implementation, providing external checkability.

Assumptions & free parameters 0 free parameters · 5 assumptions · 0 invented entities

The central claim rests on a compact timing model with several domain assumptions about macro behavior and bandwidth. No parameters are fitted to data; the bandwidth, macro size, and rewrite speed are design-space inputs. The model's integer/fractional gap is the main approximation.

assumptions (5)
  • domain assumption The compute time of a macro is time_PIM = sizemacro * nin / sizeOU, linear in the number of input vectors.
    Used in Section III to derive utilization and macro count formulas.
  • domain assumption The weight rewrite time is timerewrite = sizemacro / s at a constant per-macro speed s.
    Used throughout the latency model.
  • domain assumption Macros can be independently scheduled with arbitrary start-time offsets and no switching overhead.
    This is what makes generalized ping-pong able to pack writes; Section IV.B assumes it.
  • domain assumption The off-chip memory bandwidth is the only limiting resource; on-chip buffers and interconnect never stall.
    The model counts only off-chip bandwidth, ignoring on-chip contention.
  • domain assumption A fractional number of macros is an acceptable approximation for the integer hardware.
    Eq. (4) yields non-integer macro counts; the paper acknowledges the discrepancy in Table II.

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Cite this review

Pith. "Pith review of Generalized Ping-Pong: Off-Chip Memory Bandwidth Centric Pipelining Strategy for Processing-In-Memory Accelerators." pith.science (2026). https://pith.science/paper/N6WXO6SP

@misc{pith2026241113054,
  author       = {Pith},
  title        = {Pith review of: Generalized Ping-Pong: Off-Chip Memory Bandwidth Centric Pipelining Strategy for Processing-In-Memory Accelerators},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/N6WXO6SP}},
  note         = {Machine review of arXiv:2411.13054}
}
read the original abstract

Processing-in-memory (PIM) is a promising choice for accelerating deep neural networks (DNNs) featuring high efficiency and low power. However, the rapid upscaling of neural network model sizes poses a crucial challenge for the limited on-chip PIM capacity. When the PIM presumption of "pre-loading DNN weights/parameters only once before repetitive computing" is no longer practical, concurrent writing and computing techniques become necessary for PIM. Conventional methods of naive ping-pong or in~situ concurrent write/compute scheduling for PIM cause low utilization of off-chip memory bandwidth, subsequently offsetting the efficiency gain brought by PIM technology. To address this challenge, we propose an off-chip memory bandwidth centric pipelining strategy, named "generalized ping-pong", to maximize the utilization and performance of PIM accelerators toward large DNN models. The core idea of the proposed generalized ping-pong strategy is to evenly distribute the active time and fully utilize the off-chip memory bandwidth. Based on a programmable and scalable SRAM PIM architecture, we quantitatively analyze and compare the generalized ping-pong with the conventional scheduling strategies of naive ping-pong and in-situ write/compute for PIM. Experiments show that the generalized ping-pong strategy achieves acceleration of over 1.67 times when fully utilizing the off-chip memory bandwidth. When further limiting the off-chip memory bandwidth ranging in 8~256 bytes per clock cycle, the proposed generalized ping-pong strategy accelerates 1.22~7.71 times versus naive ping-pong. The developed PIM accelerator design with the generalized ping-poing strategy is open-sourced at https://github.com/rw999creator/gpp-pim.

Figures

Figures reproduced from arXiv: 2411.13054 by the authors.

Figure 1
Figure 1. PIM accelerators face emerging challenge in high-dimensional GeMM [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Typical SRAM-based PIM GeMM accelerator circuit block diagram [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. (a) In situ write/compute strategy. (b) Naive ping-pong strategy. (c) Generalized ping-pong strategy (this work). [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figures from the paper (3 more)
Figure 4
Figure 4. Figure 4: the specific idle time ratio of macro 32×32 bytes, the output unit size sizeOU is set to 4×8 bytes, and the bandwidth s is set to 4byte/cycle. It can be observed that only when the number of inputs nin equals 8, where timeP IM = timerewrite (i.e. matching the computing…
Figure 5
Figure 5. Figure 5: The base PIM accelerator architecture as an example to implement [PITH_FULL_IMAGE:figures/full_fig_p004_5.png]
Figure 7
Figure 7. Figure 7: (a) Scale of execution time comparison under the three strategies. [PITH_FULL_IMAGE:figures/full_fig_p006_7.png]

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Pith tools

Reviewed August 12, 2026 · model on record in the stance chip above.