REVIEW 3 major objections 4 minor 42 references
Efficient Spatio-Temporal Signal Recognition on Edge Devices Using PointLCA-Net
T0 review · 3 major / 4 minor · reviewed 2026-08-12 · deepseek-v4-flash
Pith's one-line read PointLCA-Net claims 93.41% on DVS128 with about 92% lower estimated energy than point-cloud SNNs.
desk verdict Clean proof of concept, but the 92% energy claim is not like-for-like because it excludes the feature extractor. read the letter →
The pith
A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.
The reading
What carries the argument
The central object is the Exemplar LCA-Decoder, a single-layer spiking encoder-decoder whose dictionary columns are the PointNet feature vectors $\varphi_i$. Each LIF neuron integrates an excitatory input $b_i = S\varphi_i$ and is suppressed by other active neurons through the Gramian matrix $G = \varphi^T\varphi$; a threshold $\lambda$ in Eq. (6) keeps the activation sparse, and the paper reports that about 0.4% of neurons are active at each time step. Classification uses either the maximum activation or the maximum sum of activations per class, so no trained readout layer is required. This machinery turns the deep PointNet extractor into a one-time stored dictionary and makes the per-test computation a crossbar-friendly vector-matrix product with sparse neuron activity.
What would settle it
Compute the FLOP count of the PointNet/PointNet++ feature extractor on the 1024-event DVS128 point clouds and add it to the 0.7 GFLOPs attributed to the LCA decoder; if that added cost is comparable to or larger than the decoder cost, the claimed 92% energy reduction over SpikePoint does not hold for an end-to-end deployment.
Extended reading notes
Core claim
The paper's central claim is that a dictionary of PointNet/PointNet++ features can serve as the synaptic memory of an Exemplar LCA encoder-decoder, making spatio-temporal event recognition both accurate and sparse. Training consists of extracting features once from the training point clouds and storing each feature vector as a column of a memristor crossbar; no dictionary learning or decoder backpropagation is needed. At inference, LCA dynamics—excitatory drive, Gramian inhibition, and thresholding—select a tiny fraction of active neurons, and decoding by maximum sum of per-class activations yields 98.78% on NMNIST, 78.46% on SHD, and 93.41% on DVS128 with PointNet++ features. The paper further claims that LCA sparsity cuts inference computation by an average of 99.54%, and that mapping the crossbar to an RRAM array at $9.09\times10^{-14}$ J/FLOP gives an estimated 0.065 mJ for DVS128 inference, about 24 times lower than the reported SpikePoint energy.
Load-bearing premise
The load-bearing premise is that the FLOP and energy estimates for the LCA decoder—the 0.4% active-neuron fraction and the $9.09\times10^{-14}$ J/FLOP RRAM figure—represent the deployed system's real cost, even though the paper explicitly excludes the PointNet feature-extraction stage from all accounting.
Editorial extensions
If this is right
- Across three event-based datasets (NMNIST, DVS128, SHD), the same two-stage pipeline achieves high top-1 accuracy without any backpropagation in the spiking stage.
- LCA sparsity reduces average inference computation by 99.54%, and cutting the integration interval from 100 to 10 time steps lowers inference FLOPs by roughly 80%.
- With PointNet++ features and the maximum-sum decoder, DVS128 accuracy reaches 93.41% at an estimated 0.7 GFLOPs and 0.065 mJ per inference, giving the claimed order-of-magnitude energy advantage over the point-cloud SNN baseline.
- Because the dictionary is assembled from stored features rather than learned, the same algorithm can be applied uniformly to a new spatio-temporal dataset by changing only the feature-extraction front end.
Reading between the lines
- The paper leaves implicit that the ~92% energy saving is an LCA-stage figure: adding the excluded PointNet/PointNet++ FLOPs would determine whether the saving survives at the system level, and that calculation is an immediate next step.
- The DVS128 comparison mixes protocols—PointLCA-Net uses all 11 classes with a fixed 28,606/7,408 split, while the cited 90.20% PointNet baseline used 10 classes—so a matched 10-class run would isolate how much of the gain is architectural rather than evaluational.
- The paper sketches dictionary compression (PCA, SVM, discriminative feature selection) as future work; since the dictionary holds every training point, a natural stress test is to measure accuracy and FLOPs as the dictionary is pruned on a larger continuous event stream, where the full-dictionary approach would not scale.
Editorial analysis
A structured set of objections, weighed in public.
Referee Report
Summary. The paper proposes PointLCA-Net, a two-stage pipeline for spatio-temporal signal recognition on edge devices: a pre-trained PointNet/PointNet++ extracts a 1024-dimensional global feature vector from event-based point clouds, and an Exemplar LCA encoder-decoder then performs sparse coding and classification using a dictionary of stored training features. The method is evaluated on NMNIST, DVS128, and SHD, reporting top-1 accuracies up to 98.78%, 93.41%, and 78.46% respectively. The central claim is that PointLCA-Net achieves high accuracy while reducing energy consumption by approximately 92% compared to other spiking neural networks applied to point clouds, based on FLOP estimates and an RRAM crossbar energy model.
Significance. The idea of decoupling feature extraction from a neuromorphic sparse-coding classifier is conceptually attractive and the paper is, to its credit, explicit about the experimental setup, hyperparameters, and the fact that energy numbers are theoretical estimates. The work also extends the event-cloud formulation to NMNIST and SHD for the first time, which is a useful data point. The accuracy results are on external benchmarks and the core LCA-based classification pipeline is reproducible in principle from the equations given. However, the headline energy-efficiency claim depends on an incomplete accounting of the deployed system, so the significance of the paper as a hardware-energy contribution cannot be assessed until that accounting is corrected.
major comments (3)
- [IV.E, Table II] The energy comparison against SpikePoint is not like-for-like. Section IV.E explicitly states that the FLOP estimates 'exclude the FLOPs required for feature extraction by PointNet and PointNet++,' yet Table II compares the resulting 0.065 mJ for DVS128 against SpikePoint's full-pipeline dynamic (0.82 mJ) and static (0.756 mJ) energy. The abstract's claim of 'reducing energy consumption by approximately 92%' is therefore not supported for the full system. The feature-extraction stage (PointNet with input and feature T-Nets, MLP(64,64,64,128,1024) over 1024 points) performs a substantial number of MACs that must either be added to the PointLCA-Net total or explicitly excluded from the comparison with a clear statement that the comparison is LCA-stage-only. As written, this is a load-bearing omission for the central energy-efficiency claim.
- [IV.E, Eq. (10), Table I] The sparsity estimate \hat{M}, which drives the inference FLOP count, is inherited from reference [28] with the statement 'we have verified that this estimate is accurate.' No verification data for the three datasets used here (NMNIST, DVS128, SHD) is provided. Since the '99.54% reduction in computational effort' and all derived energy numbers scale linearly with \hat{M}, the paper should report measured active-neuron fractions for each dataset and each feature extractor (PointNet vs PointNet++). If the fraction differs from 0.4%, the workload and energy conclusions change proportionally.
- [IV.F, Section V] The energy per FLOP of 9.09e-14 J is taken from Yao et al. [37], which was measured for MAC operations in a memristor CNN accelerator. PointLCA-Net's LCA decoder includes thresholding (Eq. 6), membrane potential updates (Eq. 2), and peripheral input/output circuits (Section IV.F), not only MACs. Applying the same per-FLOP figure to all these operations is an unvalidated extrapolation. The paper should either model the hardware mapping more carefully (e.g., distinguishing analog MAC energy from digital control/peripheral energy) or clearly state that the reported energy is a MAC-only lower bound. Without this, the 92% reduction claim is not robust.
minor comments (4)
- [IV.E] The equation is labeled 'F LOP s(Inf erenec)' — the word 'Inference' is misspelled; please correct the typo.
- [Table II] The footnotes 'c' and 'd' state that the PointNet/PointNet++ [4] and SpikePoint accuracies use different class counts or data partitioning. Please move these qualifications into the main text or the table caption so that the comparison is not misread as being on identical test conditions.
- [V, Table III] The hyperparameters in Table III were 'selected to achieve an accuracy near 100% when tested on the training data.' This criterion risks overfitting to the training set; please report validation-set-based selection or at least discuss the sensitivity of the reported test accuracies to the threshold λ and the number of time steps K.
- [IV.A] The description of NMNIST as 'each consisting of 300 time samples' is imprecise; NMNIST samples have varying event counts and time durations. Please rephrase to match the dataset documentation.
Circularity Check
No circular derivation: accuracy is externally benchmarked and the energy numbers are arithmetic from stated formulas, with only a non-load-bearing inherited sparsity constant.
full rationale
PointLCA-Net's accuracy is evaluated on held-out test splits of NMNIST, DVS128, and SHD, so the central accuracy claims do not reduce to a fitted parameter or to the dictionary construction by definition. The energy estimate follows from explicit FLOP formulas (Eqs. 9-10) and an external RRAM energy constant from Yao et al. [37]. The only quantity inherited from the author's prior work is the 0.4% active-neuron fraction (Section IV.E: 'According to [28], up to 0.4% of neurons spike at each time step, and we have verified that this estimate is accurate'), which is a measured sparsity figure rather than a forced theorem, and the paper states it was independently checked. The self-citations [28] and [29] supply the Exemplar LCA-Decoder architecture and FLOP-counting framework, but they are not invoked as uniqueness results, and the current pipeline adds an external benchmark evaluation. The most serious concern is an energy-accounting incompleteness, not circularity: Section IV.E explicitly says the FLOP estimates 'exclude the FLOPs required for feature extraction by PointNet and PointNet++', while Table II compares the resulting 0.065 mJ against SpikePoint's full reported dynamic and static energy. If PointNet feature extraction were a large fraction of total cost, the 92% savings claim would be overstated; however, that is an omitted-cost/correctness issue, not a case of a prediction being equivalent to its input by construction. No specific circular step can be exhibited from the paper's equations.
Assumptions & free parameters
free parameters (7)
- Threshold lambda =
0.2
- Leakage tau =
1000
- Number of time steps K =
100 (and 10 in Table I)
- Sliding window size and overlap =
0.5 s window, 0.25 s overlap
- Number of event points per sample =
1024
- Active neuron fraction =
0.4% average, with M-specific values 240, 114, 33
- Dictionary size M =
Number of training samples: 60000, 28606, 8156
assumptions (6)
- domain assumption Spatio-temporal events can be represented as 3D point clouds with coordinates (x, y, t)
- domain assumption Pretrained PointNet/PointNet++ features transfer to NMNIST, DVS128, and SHD without fine-tuning
- domain assumption The Exemplar LCA encoder-decoder with a dictionary of training features yields useful sparse codes
- standard math LCA neuron dynamics (Eq. 2 with threshold Eq. 6) converge to a sparse approximation
- domain assumption FLOP counts in Eqs. 9-10 convert linearly to energy at 9.09e-14 J/FLOP on RRAM crossbars
- ad hoc to paper PointNet feature extraction can be excluded from energy comparisons because it is performed once and stored
Cite this review
Pith. "Pith review of Efficient Spatio-Temporal Signal Recognition on Edge Devices Using PointLCA-Net." pith.science (2026). https://pith.science/paper/XDC6623V
@misc{pith2026241114585,
author = {Pith},
title = {Pith review of: Efficient Spatio-Temporal Signal Recognition on Edge Devices Using PointLCA-Net},
year = {2026},
howpublished = {\url{https://pith.science/paper/XDC6623V}},
note = {Machine review of arXiv:2411.14585}
}
read the original abstract
Recent advancements in machine learning, particularly through deep learning architectures like PointNet, have transformed the processing of three-dimensional (3D) point clouds, significantly improving 3D object classification and segmentation tasks. While 3D point clouds provide detailed spatial information, spatio-temporal signals introduce a dynamic element that accounts for changes over time. However, applying deep learning techniques to spatio-temporal signals and deploying them on edge devices presents challenges, including real-time processing, memory capacity, and power consumption. To address these issues, this paper presents a novel approach that combines PointNet's feature extraction with the in-memory computing capabilities and energy efficiency of neuromorphic systems for spatio-temporal signal recognition. The proposed method consists of a two-stage process: in the first stage, PointNet extracts features from the spatio-temporal signals, which are then stored in non-volatile memristor crossbar arrays. In the second stage, these features are processed by a single-layer spiking neural encoder-decoder that employs the Locally Competitive Algorithm (LCA) for efficient encoding and classification. This work integrates the strengths of both PointNet and LCA, enhancing computational efficiency and energy performance on edge devices. PointLCA-Net achieves high recognition accuracy for spatio-temporal data with substantially lower energy burden during both inference and training than comparable approaches, thus advancing the deployment of advanced neural architectures in energy-constrained environments.
Figures
Figures from the paper (1 more)
Reference graph
Works this paper leans on
-
[28]
D-SELD: Dataset- Scalable Exemplar LCA-Decoder
Mahmoodi Takaghaj, Sanaz, and Jack Sampson.“D-SELD: Dataset- Scalable Exemplar LCA-Decoder.” Neuromorphic Computing and En- gineering, 2024
work page 2024
-
[37]
Yao, Peng, Wu, Huaqiang, Gao, Bin, Tang, Jianshi, Zhang, Qingtian, Zhang, Wenqiang, Yang, J. Joshua, and Qian, He. Fully hardware- implemented memristor convolutional neural network . Nature, vol. 577, no. 7792, pp. 641–646, 2020. Nature Publishing Group UK London
work page 2020
-
[1]
PointNet: Deep learning on point sets for 3D classification and segmentation,
C. R. Qi, H. Su, K. Mo, and L. J. Guibas, “PointNet: Deep learning on point sets for 3D classification and segmentation,” in Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition , pp. 652–660, 2017
work page 2017
-
[2]
PointNet++: Deep hierarchical feature learning on point sets in a metric space,
C. R. Qi, L. Yi, H. Su, and L. J. Guibas, “PointNet++: Deep hierarchical feature learning on point sets in a metric space,” Advances in Neural Information Processing Systems , vol. 30, 2017
work page 2017
-
[3]
X. Ma, C. Qin, H. You, H. Ran, and Y . Fu, ”Rethinking network design and local geometry in point cloud: A simple residual MLP framework,” arXiv preprint arXiv:2202.07123 , 2022
arXiv 2022
-
[4]
Space-time event clouds for gesture recognition: From RGB cameras to event cameras,
Q. Wang, Y . Zhang, J. Yuan, and Y . Lu, “Space-time event clouds for gesture recognition: From RGB cameras to event cameras,” in 2019 IEEE Winter Conference on Applications of Computer Vision (WACV) , 2019, pp. 1826–1835
work page 2019
-
[5]
S. Dave, R. Baghdadi, T. Nowatzki, S. Avancha, A. Shrivastava, and B. Li, ”Hardware acceleration of sparse and irregular tensor computations of ML models: A survey and insights,” Proc. IEEE, vol. 109, no. 10, pp. 1706–1752, 2021
work page 2021
- [6]
Show all 42 references
-
[7]
A. Amir, B. Taba, D. Berg, T. Melano, J. McKinstry, C. Di Nolfo, T. Nayak, A. Andreopoulos, G. Garreau, M. Mendoza, and others, ”A low power, fully event-based gesture recognition system,” in Proc. IEEE Conf. Comput. Vision Pattern Recognit. , 2017, pp. 7243–7252
2017
-
[8]
Davies, N
M. Davies, N. Srinivasa, T.-H. Lin, G. Chinya, Y . Cao, S. H. Choday, G. Dimou, P. Joshi, N. Imam, S. Jain, and others, ”Loihi: A neuromorphic manycore processor with on-chip learning,” IEEE Micro, vol. 38, no. 1, pp. 82–99, 2018
2018
-
[9]
Davies, M., Wild, A., Orchard, G., Sandamirskaya, Y ., Guerra, G. A. F., Joshi, P., Plank, P., & Risbud, S. R. (2021). Advancing neuromorphic computing with Loihi: A survey of results and outlook. Proceedings of the IEEE, 109(5), 911–934. IEEE
2021
-
[10]
S. B. Furber, F. Galluppi, S. Temple, and L. A. Plana, ”The SpiNNaker project,” Proc. IEEE, vol. 102, no. 5, pp. 652–665, 2014
2014
-
[11]
Furber, S. (2016). Large-scale neuromorphic computing systems. Jour- nal of Neural Engineering , 13(5), 051001. IOP Publishing
2016
-
[12]
The SpiNNaker 2 processing element archi- tecture for hybrid digital neuromorphic computing,
S. H ¨oppner et al. , “The SpiNNaker 2 processing element archi- tecture for hybrid digital neuromorphic computing,” arXiv preprint arXiv:2103.08392, 2021
2021 arXiv
-
[13]
Schmitt, S., Kl ¨ahn, J., Bellec, G., Gr ¨ubl, A., Guettler, M., Hartel, A., Hartmann, S., Husmann, D., Husmann, K., Jeltsch, S., et al. (2017). Neuromorphic hardware in the loop: Training a deep spiking network on the BrainScaleS wafer-scale system. In 2017 International Join...
2017
-
[14]
Pehle, C., Billaudelle, S., Cramer, B., Kaiser, J., Schreiber, K., Strad- mann, Y ., Weis, J., Leibfried, A., M¨uller, E., & Schemmel, J. (2022). The BrainScaleS-2 accelerated neuromorphic system with hybrid plasticity. Frontiers in Neuroscience, 16, 795876. Frontiers Media SA
2022
-
[15]
J. Pei, L. Deng, S. Song, M. Zhao, Y . Zhang, S. Wu, G. Wang, Z. Zou, Z. Wu, W. He, and others, ”Towards artificial general intelligence with hybrid Tianjic chip architecture,” Nature, vol. 572, no. 7767, pp. 106–111, 2019
2019
-
[16]
M., K ¨ostinger, G., Nielsen, C., Qiao, N., & Indiveri, G
Richter, O., Wu, C., Whatley, A. M., K ¨ostinger, G., Nielsen, C., Qiao, N., & Indiveri, G. (2024). DYNAP-SE2: A scalable multi-core dynamic neuromorphic asynchronous spiking neural network processor. Neuro- morphic Computing and Engineering , 4(1), 014003. IOP Publishing
2024
-
[17]
Ghosh-Dastidar, S., & Adeli, H. (2009). Spiking neural networks. Inter- national Journal of Neural Systems , 19(04), 295–308. World Scientific
2009
-
[18]
Gr ¨uning, A., & Bohte, S. M. (2014). Spiking neural networks: Principles and challenges. In ESANN
2014
-
[19]
NVM neuromorphic core with 64k-cell (256-by-256) phase change memory synaptic array with on-chip neuron circuits for continuous in-situ learning,
S. Kim et al. , “NVM neuromorphic core with 64k-cell (256-by-256) phase change memory synaptic array with on-chip neuron circuits for continuous in-situ learning,” in Proc. Int. Electron Devices Meeting (IEDM), 2015, pp. 17–1
2015
-
[20]
”Nanoelectronic Programmable Synapses Based on Phase Change Materials for Brain-Inspired Computing.” Nano Letters, vol
Kuzum, Duygu, Rakesh GD Jeyasingh, Byoungil Lee, and H-S Philip Wong. ”Nanoelectronic Programmable Synapses Based on Phase Change Materials for Brain-Inspired Computing.” Nano Letters, vol. 12, no. 5, 2012, pp. 2179-2186. ACS Publications
2012
-
[21]
Detecting correlations using phase-change neurons and synapses,
T. Tuma, M. Le Gallo, A. Sebastian, and E. Eleftheriou, “Detecting correlations using phase-change neurons and synapses,” IEEE Electron Device Lett., vol. 37, no. 10, pp. 1238–1241, Oct. 2016
2016
-
[22]
Analog memristive synapse in spiking networks imple- menting unsupervised learning,
E. Covi et al., “Analog memristive synapse in spiking networks imple- menting unsupervised learning,” Front. Neurosci., vol. 10, p. 482, 2016
2016
-
[23]
All-memristive neuromorphic computing with level-tuned neurons,
A. Pantazi, S. Wo ´zniak, T. Tuma, and E. Eleftheriou, “All-memristive neuromorphic computing with level-tuned neurons,” Nanotechnology, vol. 27, no. 35, p. 355205, 2016, IOP Publishing
2016
-
[24]
M. Rao, H. Tang, J. Wu, W. Song, M. Zhang, W. Yin, Y . Zhuo, F. Kiani, B. Chen, X. Jiang, and others, ”Thousands of conductance levels in memristors integrated on CMOS,” Nature, vol. 615, no. 7954, pp. 823–829, 2023
2023
-
[25]
Unsupervised learning in probabilistic neural networks with multi-state metal-oxide memristive synapses,
A. Serb et al., “Unsupervised learning in probabilistic neural networks with multi-state metal-oxide memristive synapses,” Nature Communica- tions, vol. 7, p. 12611, 2016
2016
-
[26]
Memory devices and applications for in- memory computing
Sebastian, Abu, Le Gallo, Manuel, Khaddam-Aljameh, Riduan, and Eleftheriou, Evangelos. “Memory devices and applications for in- memory computing.” Nature Nanotechnology 15, no. 7 (2020): 529–544. Nature Publishing Group UK London
2020
-
[27]
Memory and information pro- cessing in neuromorphic systems
Indiveri, Giacomo, and Liu, Shih-Chii. “Memory and information pro- cessing in neuromorphic systems.” Proceedings of the IEEE 103, no. 8 (2015): 1379–1397. IEEE
2015
-
[29]
ViT-LCA: A Neuromorphic Approach for Vision Transformers
Mahmoodi Takaghaj, Sanaz. “ViT-LCA: A Neuromorphic Approach for Vision Transformers.” arXiv preprint arXiv:2411.00140 , 2024
2024 arXiv
-
[30]
Sparse coding via thresholding and local competition in neural circuits,
C. J. Rozell, D. H. Johnson, R. G. Baraniuk, and B. A. Olshausen, “Sparse coding via thresholding and local competition in neural circuits,” Neural Computation, vol. 20, no. 10, pp. 2526–2563, 2008
2008
-
[31]
Locally Com- petitive Algorithms for Sparse Approximation,
C. Rozell, D. Johnson, R. Baraniuk, and B. Olshausen, “Locally Com- petitive Algorithms for Sparse Approximation,” in Proc. 2007 IEEE Int. Conf. Image Processing , vol. 4, pp. IV-169–IV-172, 2007, doi: 10.1109/ICIP.2007.4379981
2007
-
[32]
Converting Static Image Datasets to Spiking Neuromorphic Datasets Using Sac- cades,
G. Orchard, A. Jayawant, G. K. Cohen, and N. Thakor, “Converting Static Image Datasets to Spiking Neuromorphic Datasets Using Sac- cades,” Frontiers in Neuroscience, vol. 9, p. 437, 2015.“
2015
-
[33]
The Heidelberg Spiking Data Sets for the Systematic Evaluation of Spiking Neural Net- works,
B. Cramer, Y . Stradmann, J. Schemmel, and F. Zenke, “The Heidelberg Spiking Data Sets for the Systematic Evaluation of Spiking Neural Net- works,” IEEE Transactions on Neural Networks and Learning Systems , vol. 33, no. 7, pp. 2744–2757, 2020
2020
-
[34]
Spiking pointnet: Spiking neural networks for point clouds,
D. Ren, Z. Ma, Y . Chen, W. Peng, X. Liu, Y . Zhang, and Y . Guo, “Spiking pointnet: Spiking neural networks for point clouds,” Advances in Neural Information Processing Systems , vol. 36, 2024
2024
-
[35]
SpikePoint: An Efficient Point-based Spiking Neural Network for Event Cameras Action Recognition,
H. Ren, Y . Zhou, X. Lin, Y . Huang, H. Fu, J. Song, and B. Cheng, “SpikePoint: An Efficient Point-based Spiking Neural Network for Event Cameras Action Recognition,” in Proc. of the Twelfth International Conference on Learning Representations , 2024
2024
-
[36]
Paszke, S
A. Paszke, S. Gross, F. Massa, A. Lerer, J. Bradbury, G. Chanan, T. Killeen, Z. Lin, N. Gimelshein, L. Antiga, and others, ”PyTorch: An imperative style, high-performance deep learning library,” Advances in Neural Information Processing Systems , vol. 32, 2019
2019
-
[38]
Point Trans- former,
H. Zhao, L. Jiang, J. Jia, P. H. S. Torr, and V . Koltun, “Point Trans- former,” in Proceedings of the IEEE/CVF International Conference on Computer Vision, pp. 16259–16268, 2021
2021
-
[39]
”Go Wider: An Efficient Neural Network for Point Cloud Analysis via Group Convolutions.” Applied Sciences, vol
Chen, Can, Luca Zanotti Fragonara, and Antonios Tsourdos. ”Go Wider: An Efficient Neural Network for Point Cloud Analysis via Group Convolutions.” Applied Sciences, vol. 10, no. 7, 2020, p. 2391. MDPI
2020
-
[40]
Khaddam-Aljameh, M
R. Khaddam-Aljameh, M. Stanisavljevic, J. F. Mas, G. Karunaratne, M. Br¨andli, F. Liu, A. Singh, S. M. M ¨uller, U. Egger, A. Petropoulos, and others, ”HERMES-core—A 1.59-TOPS/mm² PCM on 14-nm CMOS in- memory compute core using 300-ps/LSB linearized CCO-based ADCs,” IEEE J. So...
2022
-
[41]
Le Gallo, R
M. Le Gallo, R. Khaddam-Aljameh, M. Stanisavljevic, A. Vasilopoulos, B. Kersting, M. Dazzi, G. Karunaratne, M. Br ¨andli, A. Singh, S. M. Mueller, and others, ”A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference,” Nature...
2023
-
[42]
Joshua, Lu, Wei, Chang, Meng-Fan, Ielmini, Daniele, Yang, Yuchao, et al
Aguirre, Fernando, Sebastian, Abu, Le Gallo, Manuel, Song, Wenhao, Wang, Tong, Yang, J. Joshua, Lu, Wei, Chang, Meng-Fan, Ielmini, Daniele, Yang, Yuchao, et al. Hardware implementation of memristor- based artificial neural networks . Nature Communications, vol. 15, no. 1, p. 1...
1974
Reviewed August 12, 2026 · model on record in the stance chip above.
Discussion (0). Continue with ORCID to comment.