Paper Citation Record · LEDGER

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting

As of 22 August 2026, this Paper Citation Record lists 30 of 30 outbound references and 3 inbound Pith citation observations for arXiv:2411.15442.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2411.15442 v1

Coverage vector

measured 30 of 30 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-12T14:20:58.009790Z

measured 33 of 33 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-22T06:32:14.747728+00:00

measured 3 of 3 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-06-26T06:21:00.038218Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-07-04T12:39:49.528757Z

Reference resolution

30 of 30 outbound references displayed

verified exact0
verified fuzzy19
unresolved11
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation e9d53694-b143-471a-af73-673f2cc29e3c · outbound

This paper cites Autocc: Automatic discovery of covert channels in time-shared hardware,.

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting Autocc: Automatic discovery of covert channels in time-shared hardware,

Reference 1

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T14:20:58.226377Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation a80d8bd0-4477-44e0-8d33-cd2cd1729a02 · outbound

This paper cites Ieee standard for systemverilog–unified hardware design, specification, and verification language,.

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting Ieee standard for systemverilog–unified hardware design, specification, and verification language,

Reference 2

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T14:20:58.218049Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 9eca2cfd-7914-428d-85d8-625b25738424 · outbound

This paper cites Seligman, T.

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting Seligman, T

Reference 3

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T14:20:58.209785Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation f382d551-326a-45d9-af1b-2952001c14fc · outbound

This paper cites Au- tosva: Democratizing formal verification of rtl module interactions,.

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting Au- tosva: Democratizing formal verification of rtl module interactions,

Reference 4

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T14:20:58.202302Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation e51ab246-f5b9-4e31-87a5-7104d12d7793 · outbound

This paper cites Instruction-level abstraction (ila) a uniform specification for system-on-chip (soc) verification,.

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting Instruction-level abstraction (ila) a uniform specification for system-on-chip (soc) verification,

Reference 5

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T14:20:58.194656Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation b905239c-3e6f-4776-ae4e-31c8be15f538 · outbound

This paper cites Software testing with large language models: Survey, landscape, and vision,.

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting Software testing with large language models: Survey, landscape, and vision,

Reference 6

Resolution: unresolved; no resolver link, observed 2026-08-12T14:20:57.945175Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation a4f274ec-fb83-4638-92eb-c3d34fed5c05 · outbound

This paper cites (Security) Assertions by Large Language Models.

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting (Security) Assertions by Large Language Models

Reference 7

Resolution: unresolved; no resolver link, observed 2026-08-12T14:20:57.947952Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation a67cbee1-fb43-4d39-9cd3-7e1a0059bf0b · outbound

This paper cites (security) assertions by large language models,.

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting (security) assertions by large language models,

Reference 8

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T14:20:58.183005Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 0a8ebcf6-d4b6-474b-bdc5-c1c59778e39a · outbound

This paper cites Using llms to facilitate formal verification of rtl,.

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting Using llms to facilitate formal verification of rtl,

Reference 9

Resolution: unresolved; no resolver link, observed 2026-08-12T14:20:57.953374Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 0a037e21-725c-49dc-b1d6-4fa2e2343381 · outbound

This paper cites olmpics-on what language model pre-training captures,.

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting olmpics-on what language model pre-training captures,

Reference 10

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T14:20:58.172107Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation ec9209c9-e6db-4836-b213-a16e79568aec · outbound

This paper cites Are Pretrained Language Models Symbolic Reasoners Over Knowledge?.

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting Are Pretrained Language Models Symbolic Reasoners Over Knowledge?

Reference 11

Resolution: unresolved; no resolver link, observed 2026-08-12T14:20:57.958492Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation f31418c7-5d50-4c41-bc56-b07834bb14c0 · outbound

This paper cites Scaling Language Models: Methods, Analysis & Insights from Training Gopher.

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting Scaling Language Models: Methods, Analysis & Insights from Training Gopher

Reference 12

Resolution: unresolved; no resolver link, observed 2026-08-12T14:20:57.961427Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation aec7ad69-3ac6-445d-8a83-cc8e566ffbc9 · outbound

This paper cites Multi-hop Reading Comprehension through Question Decomposition and Rescoring.

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting Multi-hop Reading Comprehension through Question Decomposition and Rescoring

Reference 13

Resolution: unresolved; no resolver link, observed 2026-08-12T14:20:57.964437Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation d34b98d8-7cd3-4cce-bf0e-2c435d766692 · outbound

This paper cites Formal hardware verification with bdds: An introduction,.

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting Formal hardware verification with bdds: An introduction,

Reference 14

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T14:20:58.164856Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 73cceaa9-c649-428c-afa2-aa0edb6ae0e8 · outbound

This paper cites Formal verification in hardware design: a survey,.

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting Formal verification in hardware design: a survey,

Reference 15

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T14:20:58.156830Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 39e61a02-6492-4f3a-be21-30120c5a467c · outbound

This paper cites Less training, more repairing please: revisiting automated program repair via zero-shot learning,.

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting Less training, more repairing please: revisiting automated program repair via zero-shot learning,

Reference 16

Resolution: unresolved; no resolver link, observed 2026-08-12T14:20:57.972147Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 6a8803d7-02e8-4f2d-a057-55882fc41952 · outbound

This paper cites A syntax-guided edit decoder for neural program repair,.

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting A syntax-guided edit decoder for neural program repair,

Reference 17

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T14:20:58.144500Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation bcdab7cc-2273-4761-8857-bfdbc6baf515 · outbound

This paper cites Iter: Iterative neural repair for multi- location patches,.

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting Iter: Iterative neural repair for multi- location patches,

Reference 18

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T14:20:58.137162Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 11f54f93-332c-4c1f-ab90-25f6f35cada4 · outbound

This paper cites Goldmine: Automatic assertion generation using data mining and static analysis,.

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting Goldmine: Automatic assertion generation using data mining and static analysis,

Reference 19

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T14:20:58.129361Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 016e27ca-f801-47aa-a4cd-5fc57a5ebc03 · outbound

This paper cites Automatic genera- tion of assertions from system level design using data mining,.

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting Automatic genera- tion of assertions from system level design using data mining,

Reference 20

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T14:20:58.121926Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation e6ad2f88-b08e-442e-869e-08db653965a3 · outbound

This paper cites Word level feature discovery to enhance quality of assertion mining,.

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting Word level feature discovery to enhance quality of assertion mining,

Reference 21

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T14:20:58.113837Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 219edcb9-7dc5-43d4-962a-8639a8d5361f · outbound

This paper cites A survey on assertion- based hardware verification,.

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting A survey on assertion- based hardware verification,

Reference 22

Resolution: unresolved; no resolver link, observed 2026-08-12T14:20:57.987502Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation a5b9d9e3-d33b-46f5-84ad-8886da1ac061 · outbound

This paper cites Verigen: A large language model for verilog code generation,.

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting Verigen: A large language model for verilog code generation,

Reference 23

Resolution: unresolved; no resolver link, observed 2026-08-12T14:20:57.990801Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 471b1b74-eff3-44cb-b54b-8380a7bd7827 · outbound

This paper cites GitHub Copilot · Your AI pair programmer,.

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting GitHub Copilot · Your AI pair programmer,

Reference 24

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T14:20:58.098311Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation c9ef70a0-1a05-4f29-88bc-8b1b83bfa5d7 · outbound

This paper cites Dave: Deriving automatically verilog from english,.

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting Dave: Deriving automatically verilog from english,

Reference 25

Resolution: unresolved; no resolver link, observed 2026-08-12T14:20:57.995843Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 9131fc85-febd-4841-a317-34b211c7a738 · outbound

This paper cites (2022, Nov.) Introducing chatgpt.

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting (2022, Nov.) Introducing chatgpt

Reference 26

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T14:20:58.086233Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 0bb6960f-b2d9-4b18-ae8c-abe644395c1b · outbound

This paper cites (2023, Mar.) GPT-4.

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting (2023, Mar.) GPT-4

Reference 27

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T14:20:58.077036Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 604b2d46-ab70-4952-8e3c-be71acb8eea0 · outbound

This paper cites Systemverilog assertions (sva),.

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting Systemverilog assertions (sva),

Reference 28

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T14:20:58.069664Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 67dd520d-055a-499c-aa32-da87ca0404ac · outbound

This paper cites [Online].

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting [Online]

Reference 29

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T14:20:58.061275Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 27f8f47a-c267-4786-97e9-6b2648e6db84 · outbound

This paper cites an unresolved cited work.

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting Unresolved cited work

Reference 30

Resolution: unresolved; raw_fallback, observed 2026-08-12T14:20:58.052813Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Pith citing papers

Observation 3ea4c2b7-0f31-4699-be13-18e95a08c098 · inbound

ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs cites this paper.

ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting

Reference 28

Resolution: verified exact; arxiv_id, observed 2026-05-13T19:08:10.047602Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 2e14885b-2b24-4788-ad8f-c88c60210af5 · inbound

Automated SVA Generation with LLMs cites this paper.

Automated SVA Generation with LLMs Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting

Reference 31

Resolution: metadata mismatch; arxiv_id, observed 2026-05-11T09:06:00.676358Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation b4fea5ff-2a56-4661-aa8e-d1ae4c230ab0 · inbound

VeriPilot: An LLM-Powered Verilog Debugging Framework cites this paper.

VeriPilot: An LLM-Powered Verilog Debugging Framework Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting

Reference 35

Resolution: metadata mismatch; arxiv_id, observed 2026-07-04T12:39:49.530224Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.