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REVIEW 4 major objections 5 minor 1 cited by

High-Performance and Scalable Fault-Tolerant Quantum Computation with Lattice Surgery on a 2.5D Architecture

T0 review · 4 major / 5 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read A sparse 2.5D 'Bypass' layer shortens the effective lattice-surgery path length by a factor of $d$, removing the path-conflict and decoding bottlenecks that limit dense 2D fault-tolerant quantum computers.

desk verdict A genuinely useful architecture paper with a clever sparse Bypass layer, but the headline resource numbers rest on an unverified LER-proportionality step; conditional accept. read the letter →

arxiv 2411.17519 v1 pith:FVSWLXV4 submitted 2024-11-26 quant-ph cs.AR

Yosuke Ueno , Taku Saito , Teruo Tanimoto , Yasunari Suzuki , Yutaka Tabuchi , Shuhei Tamate , Hiroshi Nakamura This is my paper · ORCID
classification quant-phcs.AR PACS 03.67.Lx
keywords fault-tolerantquantumcomputinglatticesurgerysurfacecode2.5DarchitecturelogicalerrorrateCBPIstackphaseestimationmagicstatefactory
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper sets out to show that the main performance limiters in lattice-surgery-based fault-tolerant quantum computing—conflicting paths between operations and the decoding load of long paths—can be removed by a 2.5-dimensional layout it calls the Bypass architecture. The Bypass layout adds a sparse qubit layer beneath the dense logic layer, so distant logical qubits can be merged along short, programmably chosen routes instead of roundabout 2D paths. Because the effective path length $L'$ of a lattice-surgery operation drops by a factor of the code distance $d$, the logical error rate of the whole program falls and the code distance can be reduced. In simulations of practical quantum phase estimation programs, the proposed layout achieves a 1.73x speedup and a 17% reduction in quantum and classical hardware compared with a conventional 2D layout in the moderate-resource case. The paper also introduces the CBPI stack, a hazard-decomposition analysis that lets architects see which penalty—magic-state supply, path conflicts, or decoding—dominates execution time.

What carries the argument

The carrying mechanism is the effective path length $L'$, the number of data qubits participating in a lattice-surgery operation divided by $d^2$. In a conventional 2D merge, $L'$ grows linearly with the path length $L$ because every intermediate cell contributes $d^2$ data qubits; in the Bypass layer, a merge between distant cells uses only the $d$-wide fragments in the sparse layer, so $L'$ scales as $O(L/d)$. This reduction is what lowers both the syndrome-graph size handed to the decoder and the per-operation logical error rate. The complementary mechanism is the CBPI stack, a decomposition of average code beats per instruction into Base, Magic, Path, and Decoding components, used to identify which hazard dominates; the paper also proves that any 'immediate-operation' data-cell arrangement has a data-cell ratio at most 50%, and exhibits a 50% arrangement the Bypass layout exploits.

What would settle it

Measure, by circuit-level simulation of a full QPE program at a fixed code distance, whether the total program logical error rate is indeed proportional to the total effective path length $L'$; if cutting $L'$ by a factor of about 2 does not cut the logical error rate correspondingly, the code-distance reduction from 25 to 23 is unsupported. Alternatively, fabricate or measure an inter-layer CNOT in a flip-chip device: if its error rate exceeds about $10p$, the Bypass advantage for short lattice-surgery paths disappears, and the crossover length for benefit rises above the $L=31$ threshold reported in the paper.

Watch

Extended reading notes

Core claim

The central claim is that a dedicated sparse qubit layer can act as a programmable network for lattice surgery. In the Bypass architecture, each cell of the logic layer has a thin 'fragment' of qubits in the Bypass layer, and inter-layer CNOTs build wide-rectangle stabilizers that let a merge travel between distant cells using only $O(d^2 + Ld)$ data qubits instead of $O(Ld^2)$. Defining the effective path length as the number of data qubits involved divided by $d^2$, this turns an $O(L)$ path into an $O(L/d)$ path. Shorter paths mean lighter decoding tasks and lower logical error rates per operation; together with multiple path options that resolve conflicts, the architecture removes the path and decoding penalties that appear at dense data-cell arrangements. The paper argues, using the proportionality between program logical error rate and total effective path length, that the code distance $d$ can be lowered by 2 under practical assumptions, which is what converts improved fidelity into a 1.73x speedup and a 17% hardware reduction.

Load-bearing premise

The load-bearing premises are that the full program's logical error rate scales in direct proportion to the total effective lattice-surgery path length, and that inter-layer CNOTs can be fabricated with physical error rates no larger than about 5–10 times the intra-layer rate; if either fails, the claimed distance reduction, speedup, and resource savings do not follow.

Editorial extensions

If this is right

  • Long-range lattice-surgery merges, which dominate large QPE programs, become roughly $d$ times cheaper in the number of data qubits involved, so the advantage grows with problem size.
  • Path conflicts on a single plane disappear when one of two intersecting operations can be routed through the Bypass layer, allowing denser data-cell arrangements without path penalties.
  • Total effective path length for the Fermi-Hubbard benchmark falls to about 30% of the conventional 2D layout's value (and about half of a two-logic-layer 3D layout), which at fixed code distance lowers the program's logical error rate by the same factor.
  • With the assumed noise model and a code distance reduced from 25 to 23, the Bypass layout gives a 1.73x speedup and 17% fewer hardware resources in the moderate-resource case; in the limited-resource case the speedup is 2.35x with 13% savings.
  • The Bypass layout also reduces the variance in execution time over random logical-qubit placements, meaning less placement optimization is needed during compilation.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Because the advantage scales with the number of data cells and with the scarcity of decoding resources, the Bypass gain is likely to widen for larger FTQC programs or for cryogenic decoder budgets, an extrapolation beyond the simulated benchmarks.
  • The same sparse-layer idea could be applied to other topological codes or to neutral-atom or photon-based hardware, but only if inter-layer two-qubit gates can be kept close to intra-layer error rates; the paper's assumptions suggest an experimental requirement of physical error rate $p' \lesssim 10p$.
  • The CBPI stack could be used as an iterative design loop: measure which hazard dominates, change the architecture, and re-measure; extending it to include factory decoding or non-greedy schedulers would be a natural next step not carried out here.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. The paper introduces the CBPI stack, a bottleneck-analysis methodology for lattice-surgery-based fault-tolerant quantum computing, and proposes the Bypass architecture, a 2.5D layout with a dense Logic layer and a sparse Bypass layer. The authors define an effective path length L', argue that the Bypass layer reduces L' by a factor of the code distance d, and evaluate the architecture with circuit-level Stim/PyMatching simulations for MEAS_ZZ operations and a cycle-accurate LS simulator on quantum phase estimation benchmarks. The central quantitative claims are a 1.73x speedup and a 17% reduction in quantum/classical hardware resources over a conventional 2D layout in the moderate-resources case, obtained after reducing the code distance from 25 to 23 on the basis of the reduced total effective path length.

Significance. If the central claims hold, the Bypass architecture is a plausible route to higher-density and lower-overhead lattice-surgery computation, and the CBPI stack is a useful organizing framework for architecture-level FTQC performance analysis. The paper has several concrete strengths: circuit-level LER simulations with Stim and PyMatching, systematic sweeps over nF, TPdec, Rdata, and problem size, 1000 random qubit assignments with reported standard deviations, and a clean proof in Appendix A that 50% is the maximum data-cell ratio for immediate-operation-capable arrangements. The central resource-reduction claim, however, rests on an extrapolation from total effective path length to program-wide logical error rate that is asserted rather than demonstrated; this is the main load-bearing point that needs additional validation.

major comments (4)
  1. [Sec. 7.3 ("LS path length and program fidelity")] The reduction from d=25 to d=23 is not supported by a calculated or simulated program-wide logical error rate. The text cites p_L ≈ const × (p/p_th)^((d-1)/2) for a single logical operation and then asserts that the LER of the entire FTQC program is proportional to the total effective path length of all LS operations; no derivation is given, and the aggregate L' histograms in Fig. 13 are not a program-LER computation. This assumption must be checked by simulating the full QPE program (or a representative subset, including magic-state teleportation and the factory decoding that is currently excluded in Sec. 7.2) at d=25 and d=23, or by deriving a bound from the per-operation LER curves in Fig. 10. Until this check is done, the 17% resource reduction and 1.73x speedup in Sec. 7.5 rest on an unverified scaling hypothesis.
  2. [Sec. 7.2 (decoding model)] The conclusion that the Bypass architecture eliminates or reduces the decoding penalty depends on the assumption that "the decoding task difficulty for a single cell in the Bypass layer is 1/d of that for a single cell in the Logic layer." This is a modeling choice, not a measured or simulated decoder cost. The inter-layer stabilizers have 6-degree connectivity and a different syndrome-graph geometry, so the 1/d factor needs justification with decoder-level data (e.g., matching-graph size or PyMatching runtime) or at least a sensitivity analysis. Since the CBPI results in Figs. 14-17 are directly affected by the decoding-penalty term, this assumption is load-bearing for the reported speedups.
  3. [Sec. 6.2 and Sec. 5.2.2] The LER advantage of the Bypass layer is shown only for MEAS_ZZ operations above a crossover path length; for the pessimistic p'=10p case, Fig. 10(d) places the crossover at L≥31. The paper does not report the distribution of actual LS path lengths L for the benchmark programs, only the effective path length L' in Fig. 13, so it is not established that a sufficiently large fraction of operations in FH(200) lie above this crossover for the aggregate fidelity improvement to hold. Please report the program-level distribution of L and compute the total program LER under p'=5p and p'=10p, rather than relying on the MEAS_ZZ-only comparison.
  4. [Sec. 7.5 (Fig. 17)] The purple-star curves for d=23 appear to be obtained by rescaling the resource axis of the d=25 cycle-accurate simulations, but the simulation model couples code distance to decoder throughput (TPdec per cell), decoding-task difficulty, and the Bypass-layer 1/d factor, so it is not obvious that CBPI remains unchanged when d changes from 25 to 23. The authors should rerun the LS simulation at d=23 for the reported configurations, or explicitly argue why CBPI is invariant under this change; otherwise the resource/performance trade-off curves for d=23 are extrapolations.
minor comments (5)
  1. [Sec. 5.2.2] The definition of L' as "the number of data qubits involved in a given LS instruction divided by d^2" would benefit from a sentence explaining why this dimensionless quantity is called an effective path length; as written it can be mistaken for an area or volume measure.
  2. [Fig. 13 caption and legend] The legend values "Acc." and "Ave." should be defined in the caption; "Acc." appears to denote the total accumulated L' over the program, but this is not stated.
  3. [Sec. 3.2.2 and Sec. 7.2] The main text says factories generate magic states at "regular intervals of several code beats," while Sec. 7.2 specifies 15 code beats per MSD circuit; please make the main-text description consistent with the simulation parameter.
  4. [Sec. 7.2] The relationship between TPdec and per-cell decoding capacity is described verbally as "0.5 (1.0) ... half (all) of the cells"; stating this as an explicit equation would improve reproducibility of the cycle-accurate simulator.
  5. [General] No artifact availability statement is given for the Stim circuits or the cycle-accurate LS simulator; releasing code and data would substantially strengthen verification of the d=23 extrapolation and the CBPI results.

Circularity Check

0 steps flagged · score 2.0 of 10

No circular derivation: the central speedup and resource claims come from direct layout simulations under stated assumptions, while the d=23 extrapolation is an explicit scaling assumption rather than a fitted or self-citation-based prediction.

full rationale

The paper's central results, the 1.73x speedup and 17% resource reduction, are obtained from a cycle-accurate lattice-surgery simulator that compares four qubit layouts under the same stated greedy scheduling policy and with swept, not fitted, parameters (nF, TPdec, Rdata). The CBPI stack is an accounting decomposition in which the Base CBPI is simulated with hazards disabled and each penalty is the residual difference from adding that hazard; the sum equals the total CBPI by construction, and the paper explicitly acknowledges the known difficulty of accurate multi-hazard CPI-style decomposition and leaves it as future work. The claimed L' reduction by a factor of d in Sec. 5.2.2 follows by counting data qubits in the authors' own geometry, so it is an architectural property rather than a fitted result. The circuit-level LER simulations in Sec. 6 use Stim and PyMatching with stated inter-layer PER assumptions (p' = p, 5p, 10p) taken from flip-chip references, and these simulations are independent of the architecture-level scheduling claims. The only load-bearing scaling step is Sec. 7.3, where the total program LER is assumed to be proportional to the total effective path length L', and this assumption converts the L' histograms of Fig. 13 into a code-distance reduction of 2 and hence the d=23 resource numbers. That step is an explicit, unverified modeling assumption and a validation gap, especially since factory decoding is excluded and program-level proportionality is not tested, but it is not a circular reduction: no parameter is fitted to the target result, and the d=23 point is presented as an extrapolation rather than as an independent measured prediction. The self-citations [45-47] appear only as background support for the claim that decoders in cryogenic environments must be resource-efficient, and they are not load-bearing for the Bypass performance claims. Overall, the derivation chain is not circular, with only minor non-circular validation concerns.

Assumptions & free parameters 6 free parameters · 5 assumptions · 1 invented entities

The central claim rests on several modeling and hardware assumptions: the LER proportionality that justifies code-distance reduction, the decoder difficulty model, the assumed inter-layer error rate, and the feasibility of flip-chip 2.5D integration. These are stated or cited but not independently validated, so they are listed as free parameters and domain assumptions.

free parameters (6)
  • p' (inter-layer physical error rate) = p, 5p, 10p
    PER of inter-layer CNOTs in the Bypass layer; assumed from flip-chip bonding references and swept, not measured in this work.
  • TPdec (decoding throughput per cell) = 0.4, 0.45, 0.5, 0.6, 0.8, 1.0
    Modeled decoder capacity per code beat per cell; swept to test sensitivity, not fitted to hardware.
  • p (physical error rate) = 0.001 for LER sweeps, 0.003 for d reduction
    Input physical error rate assumed for superconducting hardware; central to the threshold-based d reduction argument.
  • Code distance d = 25 baseline, 23 proposed
    Baseline from Ref. [49]; reduction by 2 is derived from the assumed LER proportionality, not from a full program simulation.
  • nF (number of MSD circuits) = 4, 8, 12, 16
    Number of magic-state distillation circuits; swept to test performance sensitivity.
  • Bypass wide arrangement height = optimized per cell count
    Height chosen to minimize average effective path length L' in Fig. 12(b); a design optimization rather than a fitted constant.
assumptions (5)
  • domain assumption Logical error rate per operation scales as const*(p/p_th)^((d-1)/2), and total program LER is proportional to total LS path length.
    Sec 7.3 uses this to justify reducing d from 25 to 23; factory operations and non-LS components are not included in the path-length sum.
  • domain assumption Decoding task difficulty is proportional to the number of data qubits involved and operation duration, with Bypass-layer cells weighted 1/d.
    Sec 7.2 decoder queue model; no actual decoder implementation or latency model is validated against hardware.
  • domain assumption Circuit-level depolarizing noise after every gate plus measurement errors captures the hardware behavior.
    Sec 6.1; standard in QEC simulation but an idealization of real device noise.
  • domain assumption IO-capable data cell arrangements require conditions (I) and (II), and any such arrangement has Rdata less than 1/2.
    Appendix A; the theorem is stated for a finite patch, and the new 50% arrangement is the infinite-periodic limit.
  • domain assumption Flip-chip bonding, TSVs, and 6-degree qubit connections can be fabricated without compromising Logic-layer density.
    Sec 5.3 and Fig. 8 argue feasibility from prior fabrication work, but the specific 2.5D stack is not demonstrated.
invented entities (1)
  • Bypass layer (sparse SC fragment layer)
    purpose: Provide horizontal LS paths with effective path length O(L/d) and multiple path options to reduce path and decoding hazards.
    Proposed architectural component evaluated only in simulation; no fabricated device or independent measurement exists.

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Cite this review

Pith. "Pith review of High-Performance and Scalable Fault-Tolerant Quantum Computation with Lattice Surgery on a 2.5D Architecture." pith.science (2026). https://pith.science/paper/FVSWLXV4

@misc{pith2026241117519,
  author       = {Pith},
  title        = {Pith review of: High-Performance and Scalable Fault-Tolerant Quantum Computation with Lattice Surgery on a 2.5D Architecture},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/FVSWLXV4}},
  note         = {Machine review of arXiv:2411.17519}
}
read the original abstract

Due to the high error rate of a qubit, detecting and correcting errors on it is essential for fault-tolerant quantum computing (FTQC). Among several FTQC techniques, lattice surgery (LS) using surface code (SC) is currently promising. To demonstrate practical quantum advantage as early as possible, it is indispensable to propose a high-performance and low-overhead FTQC architecture specialized for a given FTQC scheme based on detailed analysis. In this study, we first categorize the factors, or hazards, that degrade LS-based FTQC performance and propose a performance evaluation methodology to decompose the impact of each hazard, inspired by the CPI stack. We propose the Bypass architecture based on the bottleneck analysis using the proposed evaluation methodology. The proposed Bypass architecture is a 2.5-dimensional architecture consisting of dense and sparse qubit layers and successfully eliminates the bottleneck to achieve high-performance and scalable LS-based FTQC. We evaluate the proposed architecture with a circuit-level stabilizer simulator and a cycle-accurate LS simulator with practical quantum phase estimation problems. The results show that the Bypass architecture improves the fidelity of FTQC and achieves both a 1.73x speedup and a 17% reduction in classical/quantum hardware resources over a conventional 2D architecture.

Figures

Figures reproduced from arXiv: 2411.17519 by the authors.

Figure 1
Figure 1. FTQC performance evaluation using CBPI stack for [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 3
Figure 3. (a) Stabilizer-level picture of SC (𝑑 = 5). (b) Merge operation for MEAS_ZZ instruction (Stabilizer-level view). (c) Cell- and stabilizer-level views of qubit plane during MEAS_XX instruction. on the two logical qubits. The outcome of the logical Pauli mea￾surement is calculated from the parity of the outcomes of Pauli-𝑋 stabilizer measurements in the first cycle of LS. The Pauli-𝑋𝑋 mea￾surement can also be performe… view at source ↗
Figure 4
Figure 4. Procedure of each instruction in Table [PITH_FULL_IMAGE:figures/full_fig_p003_4.png] view at source ↗
Figures from the paper (12 more)
Figure 5
Figure 5. Figure 5: (a) Path hazard caused by two LS operations. (b) Magic hazard. (c) A gate-teleportation circuit to perform [PITH_FULL_IMAGE:figures/full_fig_p004_5.png]
Figure 6
Figure 6. Figure 6: (a) A 3D view of the Bypass architecture. (b) Inter-layer stabilizer in the circled area of (a) and its 3D qubits placement. [PITH_FULL_IMAGE:figures/full_fig_p006_6.png]
Figure 7
Figure 7. Figure 7: LS operation with and without Bypass layer. [PITH_FULL_IMAGE:figures/full_fig_p006_7.png]
Figure 8
Figure 8. Figure 8: Implementation of the Bypass architecture. (a) Side view. (b) Top view. (c) Bird’s-eye view of the shadowed part of (b). [PITH_FULL_IMAGE:figures/full_fig_p007_8.png]
Figure 9
Figure 9. Figure 9: Use of Bypass with different code distances. [PITH_FULL_IMAGE:figures/full_fig_p007_9.png]
Figure 10
Figure 10. Figure 10: (a), (b) LER of MEAS_ZZ operations with and without Bypass layer. (c) Relative LER of bypassing MEAS_ZZ relative to that without Bypass layer and its sensitivity to 𝐿. (d) Crossover path length 𝐿 where the Bypass layer improves LER [PITH_FULL_IMAGE:figures/full_fig_p…
Figure 11
Figure 11. Figure 11: (a) Qubit layouts. (b) Floor plan and data cell ar [PITH_FULL_IMAGE:figures/full_fig_p009_11.png]
Figure 13
Figure 13. Figure 13: Histogram of 𝐿 ′ for QPE program with FH (200). pathway layer to avoid roundabout paths, leading to a reduction in 𝐿 ′ as 𝑅𝑑𝑎𝑡𝑎 increases. For sparse data cell arrangements with 𝑅𝑑𝑎𝑡𝑎 = 25%, where no roundabout paths exist even in the 1L-D layout, the average 𝐿 ′ is n…
Figure 15
Figure 15. Figure 15: CBPI stacks of QPE FH model with 𝑁𝑠𝑖𝑧𝑒 = 200. Since [PITH_FULL_IMAGE:figures/full_fig_p010_15.png]
Figure 16
Figure 16. Figure 16: CBPI sensitivity results for QPE with FH models. [PITH_FULL_IMAGE:figures/full_fig_p011_16.png]
Figure 17
Figure 17. Figure 17: Tradeoff between CBPI and the number of physical qubits in the Cells and Pools parts. [PITH_FULL_IMAGE:figures/full_fig_p012_17.png]
Figure 18
Figure 18. Figure 18: IO-capable and incapable arrangements with data [PITH_FULL_IMAGE:figures/full_fig_p012_18.png]

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Forward citations

Cited by 1 Pith paper

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