Paper Citation Record · LEDGER

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors

As of 13 August 2026, this Paper Citation Record lists 38 of 38 outbound references and 0 inbound Pith citation observations for arXiv:2411.18114.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2411.18114 v1

Coverage vector

measured 38 of 38 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-12T11:35:32.605432Z

measured 38 of 38 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-12T06:34:41.77262+00:00

measured 0 of 0 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: cited_works

Reference resolution

38 of 38 outbound references displayed

verified exact0
verified fuzzy36
unresolved2
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation ce1d63a1-cce8-478b-a899-0625f9302ea7 · outbound

This paper cites 1 are turned off, giving rise to the leakage currents I S1 and I S2 respectively.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors 1 are turned off, giving rise to the leakage currents I S1 and I S2 respectively

Reference 1

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:33.188265Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation 4c10b56d-e5fc-41c8-a3da-8fff7b79ce5b · outbound

This paper cites an unresolved cited work.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors Unresolved cited work

Reference 2

Resolution: unresolved; raw_fallback, observed 2026-08-12T11:35:33.173050Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation 4e80259f-e171-4895-b363-a3b311729194 · outbound

This paper cites an unresolved cited work.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors Unresolved cited work

Reference 3

Resolution: unresolved; raw_fallback, observed 2026-08-12T11:35:33.157813Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation 823f80bd-795b-4636-87c1-9c1026bfd5d0 · outbound

This paper cites [Online].

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors [Online]

Reference 4

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:33.142761Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation 89800315-2ecb-47ca-98ee-0b25e62d659d · outbound

This paper cites Scale changes in electronics: Implications for nanostructure devices for logic and memory and beyond,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors Scale changes in electronics: Implications for nanostructure devices for logic and memory and beyond,

Reference 5

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:33.127937Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation 9bf60924-6a7a-4bc4-a257-0651f36d69bf · outbound

This paper cites A 14 nm FinFET 128 Mb SRAM With Vmin enhancement techniques for low-power Applications,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors A 14 nm FinFET 128 Mb SRAM With Vmin enhancement techniques for low-power Applications,

Reference 6

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:33.113608Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation 0096abca-5d2b-44b0-8cfe-2c3e9a6944cb · outbound

This paper cites Cheng, S.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors Cheng, S

Reference 7

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:33.098876Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation bc729560-7f4c-468f-8703-41dadb9602fc · outbound

This paper cites A sub-600-mV, fluctuation tolerant 65-nm CMOS SRAM array with dynamic cell biasing,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors A sub-600-mV, fluctuation tolerant 65-nm CMOS SRAM array with dynamic cell biasing,

Reference 8

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:33.083682Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation 3877eae6-5ffe-4924-8fd1-fe6c10a02586 · outbound

This paper cites Digital circuit design challenges and opportunities in the era of nanoscale CMOS,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors Digital circuit design challenges and opportunities in the era of nanoscale CMOS,

Reference 9

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:33.069377Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation 72cc2b9b-6690-42c6-bdca-ed942e9ca508 · outbound

This paper cites A voltage scalable 0.26 V, 64 kb 8T SRAM with V min lowering techniques and deep sleep mode,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors A voltage scalable 0.26 V, 64 kb 8T SRAM with V min lowering techniques and deep sleep mode,

Reference 10

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:33.054481Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation 849b382f-13a8-469b-bac6-ad4c5ecb6cdd · outbound

This paper cites Design and analysis of a 32nm PVT tolerant CMOS SRAM cell for low leakage and high stability.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors Design and analysis of a 32nm PVT tolerant CMOS SRAM cell for low leakage and high stability

Reference 11

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:33.039735Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation 18962f62-b555-419e-b8fd-c13f4b3f7fa9 · outbound

This paper cites Sub-threshold 10T SRAM bit cell with read/write XY selection,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors Sub-threshold 10T SRAM bit cell with read/write XY selection,

Reference 12

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:33.024770Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation e5826423-c6ed-479a-96da-da69fb52cc1b · outbound

This paper cites A read -static-noise-margin-free SRAM cell for low-VDD and high-speed applications,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors A read -static-noise-margin-free SRAM cell for low-VDD and high-speed applications,

Reference 13

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:33.010549Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation ecf20129-022b-4bd9-8ff0-49faaa16476e · outbound

This paper cites A 256 kb sub-threshold SRAM in 65 nm CMOS,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors A 256 kb sub-threshold SRAM in 65 nm CMOS,

Reference 14

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:32.995983Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation 64bd7b98-4d81-4d1f-9a4c-81a0e0937491 · outbound

This paper cites A 45nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors A 45nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues,

Reference 15

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:32.980298Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation 19c23854-45ed-4096-94d2-8d1e9e6b8a87 · outbound

This paper cites A discussion on SRAM circuit design trend in deeper nanometer-scale technologies,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors A discussion on SRAM circuit design trend in deeper nanometer-scale technologies,

Reference 16

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:32.965943Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation e7a028ab-b9e4-49e5-bb30-f3ce17fec41e · outbound

This paper cites A 5.3 GHz 8T-SRAM with operation down to 0.41 V in 65 nm CMOS,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors A 5.3 GHz 8T-SRAM with operation down to 0.41 V in 65 nm CMOS,

Reference 17

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:32.951951Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation 71d60303-6158-443e-8c94-de2407a7493b · outbound

This paper cites Impact of circuit assist methods on margin and performance in 6T SRAM,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors Impact of circuit assist methods on margin and performance in 6T SRAM,

Reference 18

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:32.937905Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation dc0ff494-4c14-4bd8-bb5f-453f7922d4c8 · outbound

This paper cites On the efficacy of write- assist techniques in low voltage nanoscale SRAMs,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors On the efficacy of write- assist techniques in low voltage nanoscale SRAMs,

Reference 19

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:32.923841Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation 90e0872e-b4da-42da-a52d-7cf7faf8dff0 · outbound

This paper cites A cross-layer framework for designing and optimizing deeply-scaled FinFET- based SRAM cells under process variations,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors A cross-layer framework for designing and optimizing deeply-scaled FinFET- based SRAM cells under process variations,

Reference 20

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:32.909498Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation 1454f06e-64c1-4bdf-9475-a76137a85a89 · outbound

This paper cites FinFET based SRAM design: a survey on device, circuit, and technology Issues,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors FinFET based SRAM design: a survey on device, circuit, and technology Issues,

Reference 21

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:32.895165Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation 8b90195d-e489-4cd2-93be-34938c946a5b · outbound

This paper cites 0.4-V logic-library- friendly SRAM array using rectangular-diffusion cell and delta- boosted-array voltage scheme,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors 0.4-V logic-library- friendly SRAM array using rectangular-diffusion cell and delta- boosted-array voltage scheme,

Reference 22

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:32.880872Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation 107556e3-abaa-470a-b3ff-b251e0eaeefa · outbound

This paper cites Ohbayashi, M.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors Ohbayashi, M

Reference 23

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:32.866357Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation f8ead562-1940-460f-9a55-f2a6a5f469f9 · outbound

This paper cites Matching Properties of MOS Transistors,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors Matching Properties of MOS Transistors,

Reference 24

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:32.852806Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation 3af557b9-958a-4d48-b36e-05f3159d66c9 · outbound

This paper cites Fluctuation limits and scaling opportunities for CMOS SRAM cells,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors Fluctuation limits and scaling opportunities for CMOS SRAM cells,

Reference 25

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:32.838993Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation a11b41ca-8c45-4587-af2b-1427182f30de · outbound

This paper cites An experimental approach to accurate alpha-SER modeling and optimization through design parameters in 6T SRAM cells for deep-nanometer CMOS,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors An experimental approach to accurate alpha-SER modeling and optimization through design parameters in 6T SRAM cells for deep-nanometer CMOS,

Reference 26

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:32.825199Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation cb6f67e3-5f57-49d4-b3d5-059eb1d98ad4 · outbound

This paper cites A design-oriented soft error rate variation model accounting for both die-to-die and within-die variations in submicrometer CMOS SRAM cells,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors A design-oriented soft error rate variation model accounting for both die-to-die and within-die variations in submicrometer CMOS SRAM cells,

Reference 27

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:32.811110Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation ad19743a-85fb-4093-8ab7-6f2cd9c4ee8e · outbound

This paper cites Large-Scale SRAM Variability Characterization in 45 nm CMOS,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors Large-Scale SRAM Variability Characterization in 45 nm CMOS,

Reference 28

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:32.796849Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation 7527d03f-dc64-4c39-8c12-2d1f46eccdf2 · outbound

This paper cites Accurate modeling od dynamic variability of SRAM cell in 28 nm FDSOI technology,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors Accurate modeling od dynamic variability of SRAM cell in 28 nm FDSOI technology,

Reference 29

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:32.782263Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation a0079a63-2bc3-4fe3-b1ad-2301f601eb27 · outbound

This paper cites Application-specific selection of 6T SRAM cells offering superior performance and quality with triple- threshold-voltage CMOS technology,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors Application-specific selection of 6T SRAM cells offering superior performance and quality with triple- threshold-voltage CMOS technology,

Reference 30

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:32.767270Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation ffd6e137-0c7c-4249-acba-1c956094c12b · outbound

This paper cites A 4.6 Ghz 162 Mb SRAM design in 22 nm tri-gate CMOS technology with integrated read and write assist circuitry,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors A 4.6 Ghz 162 Mb SRAM design in 22 nm tri-gate CMOS technology with integrated read and write assist circuitry,

Reference 31

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:32.752161Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation 2f295503-f8e8-49f8-b5e2-7b2819065889 · outbound

This paper cites Adaptive static and dynamic noise margin improvement in minimum-sized 6T- SRAM cells,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors Adaptive static and dynamic noise margin improvement in minimum-sized 6T- SRAM cells,

Reference 32

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:32.737147Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation 66d401a3-dde2-47fe-84ac-57eec1fd66fd · outbound

This paper cites Soft-Error performance evolution on emergint low power devices,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors Soft-Error performance evolution on emergint low power devices,

Reference 33

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:32.721538Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation 86d7f3f8-0a40-47ab-9635-1ea56aa92201 · outbound

This paper cites Thermal neutron-induced soft errors in advanced memory and logic devices,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors Thermal neutron-induced soft errors in advanced memory and logic devices,

Reference 34

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:32.705247Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation 3fd97e3f-b3a4-4912-95f6-8bc049dc6e3a · outbound

This paper cites Impact of CMOS technology scaling on the atmospheric neutron soft error rate,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors Impact of CMOS technology scaling on the atmospheric neutron soft error rate,

Reference 35

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:32.691013Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation a53e891e-2377-4787-bd0f-2ad1b7d1e7bd · outbound

This paper cites Detailed 8- transistor SRAM cell analysis for improved alpha particle radiation hardening in nanometer technologies,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors Detailed 8- transistor SRAM cell analysis for improved alpha particle radiation hardening in nanometer technologies,

Reference 36

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:32.674412Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation 1f1a03c5-9833-4f5f-be46-5ea49df7c59b · outbound

This paper cites A comprehensive study on the soft-error rate of flip-flops from 90- nm production libraries,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors A comprehensive study on the soft-error rate of flip-flops from 90- nm production libraries,

Reference 37

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:32.659344Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation 0de36e81-34ec-4e7e-b5d0-7f3d33c3f061 · outbound

This paper cites SRAM Design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction,.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors SRAM Design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction,

Reference 38

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T11:35:32.642715Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Pith citing papers

No inbound Pith citation observations are available.