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REVIEW 3 major objections 7 minor 55 references

Leveraging Hardware Power through Optimal Pulse Profiling for Each Qubit Pair

T0 review · 3 major / 7 minor · reviewed 2026-08-12 · deepseek-v4-flash

Pith's one-line read This paper establishes that profiling each qubit pair with its own optimal two-qubit pulse waveform—selected from three candidates—reduces median gate error by 1.84x and doubles quantum volume on 127-qubit IBM processors.

desk verdict Real-machine calibration protocol with three pulse waveforms and three profiling policies shows real improvements on 127-qubit IBM devices, but the headline median-error claim is under-specified and the QEC threshold conclusion is overstated. read the letter →

arxiv 2411.19308 v1 pith:K4NIDJGC submitted 2024-11-28 quant-ph

classification quant-ph MSC 81P6881-05 PACS 03.67.-a85.25.-j
keywords pulseprofilingcross-resonancegatemulti-derivativeDRAGdirectCRheavy-hextopologyparallelcalibrationquantumvolumetwo-qubiterror
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper tries to establish that two-qubit gate calibration on large superconducting processors should be done per qubit pair, not with one pulse shape for all pairs. It enlarges the candidate set for the echoed cross-resonance (ECR) gate to three waveforms—echoed CR, multi-derivative DRAG, and direct CR—and assigns each pair the waveform best suited to its physical properties, heavy-hex topology position, and coherence limits. On 127-qubit IBM processors the protocol reports a median two-qubit gate error of $4.4\times 10^{-3}$, a 1.84x improvement over the default pulse configuration, a doubling of quantum volume from 128 to 256, and up to a 2.3x reduction in error per layered gate. The payoff of the claim is that existing hardware can be pushed closer to the error threshold where quantum error correction begins to suppress errors, without waiting for new chip designs.

What carries the argument

The load-bearing object is the echoed cross-resonance (ECR) two-qubit gate, realized by any of three microwave pulse waveforms: the standard echoed CR pulse, a multi-derivative DRAG pulse that suppresses multiple transition errors through recursive derivative corrections, and a direct CR pulse that is shorter but costlier to calibrate. The profiling step maps each qubit pair to its preferred waveform using either physics-based clustering, heavy-hex unit-cell position, or hardware knowledge such as frequency detuning and coherence times. The parallel-calibration step partitions the coupling graph $\mathcal{G}$ into calibration subgraphs in which concurrently calibrated edges are separated by a minimum graph distance of two, enabling up to 38 pairs to be calibrated at once on the 127-qubit heavy-hex layout. Together, waveform assignment plus subgraph-parallel calibration is the mechanism that converts per-pair optimization into processor-wide gate-error reduction.

What would settle it

Measure all three candidate waveforms with interleaved randomized benchmarking on every pair of a 127-qubit heavy-hex processor and compare the policy-assigned waveform to the measured best waveform. If the assigned waveform is not the lowest-error one for most pairs, the claim of per-pair optimal profiling fails; the paper's own Figure 12 already reports misses on 5 of 21 pairs with Brute-force Clustering and 2 of 21 with Topology-oriented Representative.

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Extended reading notes

Core claim

The central claim is that per-qubit-pair pulse profiling—selecting, for each coupled pair, one of three calibrated ECR waveforms—delivers fidelity gains that survive at the device level, not just on individually tuned pairs. The paper demonstrates this with three profiling policies: a clustering policy grouping pairs by frequency detuning, coupling strength, and anharmonicity; a topology policy exploiting the repeating unit-cell structure of the heavy-hex lattice; and a hardware-oriented policy that also accounts for qubit-qubit detuning ranges and $T_1$/$T_2$ decoherence times. After calibration, the median two-qubit gate error on the real machine drops to $4.4\times 10^{-3}$, a 1.84x improvement relative to the vendor default, while the minimum error reaches $1.3\times 10^{-3}$. On two 127-qubit processors the quantum volume doubles from 128 to 256 and the error per layered gate falls by factors of 2.3 and 1.99. The paper reads these results as evidence that the protocol captures hardware-specific differences that uniform calibration misses, and that this is an immediate step toward operating below the error-correction threshold.

Load-bearing premise

The protocol assumes that a pulse calibrated on one representative qubit pair remains the optimal choice for every other pair assigned to the same cluster or the same heavy-hex unit-cell position.

Editorial extensions

If this is right

  • If the reported numbers hold, a calibration pass that selects among three pulse waveforms can push 127-qubit processors from quantum volume 128 to 256 without any change in chip fabrication.
  • The minimum two-qubit gate error of $1.3\times 10^{-3}$ lies below the $3\times 10^{-3}$ threshold the paper cites for error correction on the heavy-hex lattice, so the protocol moves surface-code operation closer to the error-suppression regime.
  • Because calibration subgraphs allow up to 38 pairs to be calibrated concurrently, routine recalibration becomes affordable: the paper reports a 7.9x reduction in calibration wall-clock time in practice and up to 25x under ideal hardware, meaning drift can be countered more often.
  • Application-level benchmarks on standard quantum circuits all show lower error rates and higher fidelities after calibration, with a maximum fidelity increase of 16%, indicating the gain reaches compiled user programs.
  • Shorter direct CR pulses reduce total pulse duration by a factor of 1.26 for pairs with fabrication defects or short coherence times, extending how many sequential entangling gates fit within the decoherence limit.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The paper's own benchmarking shows the representative-based profiling is not truly per-pair optimal: 5 of 21 pairs receive a non-optimal waveform under Brute-force Clustering and 2 of 21 under Topology-oriented Representative. A hybrid protocol that spot-checks a second waveform on outlier pairs would likely close most of that gap.
  • The three waveforms trade fidelity against calibration cost and duration, so the optimal assignment will drift as qubits age; an online re-profiling step that periodically re-measures a small sample of pairs could maintain the reported gains over time.
  • The profiling logic is tied to cross-resonance gates on fixed-frequency superconducting qubits with heavy-hex layouts; porting it to tunable qubits or other two-qubit gate families would require re-deriving the feature set and the waveform candidates, though the subgraph-parallelization idea transfers directly.
  • The parallel-calibration speedup is bounded by hardware limits on concurrent arbitrary waveforms (the paper splits subgraphs larger than 20 edges into groups of no more than 10), so the ideal 25x reduction would need controller hardware that handles many custom pulses simultaneously.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 7 minor

Summary. The manuscript proposes a fine-grained calibration protocol for two-qubit ECR gates on IBM heavy-hex superconducting processors. It enlarges the pulse candidate set to three waveforms (echoed CR, multi-derivative DRAG, direct CR), introduces three policies for profiling each qubit pair's optimal waveform (Brute-force Clustering, Topology-oriented Representative, Hardware-oriented Policy), and adds a graph-based parallel calibration scheme. The protocol is evaluated on 127-qubit machines (ibm_rensselaer, ibm_nazca, ibm_strasbourg) with gate-level IRB measurements, calibration-time measurements, device-level QV and EPLG benchmarks, and application-level circuits. The headline claims are a 1.84x reduction in median two-qubit gate error, a doubling of quantum volume, up to 2.3x reduction in EPLG, and that the minimum error falls below a QEC threshold.

Significance. If the central claims hold, this is a practically useful engineering contribution: it demonstrates per-qubit-pair pulse profiling with multiple waveform types on real IBM hardware, and it backs the claims with machine-measured gate-level and device-level benchmarks. The paper deserves credit for reporting IRB measurements, QV and EPLG results in Table I, and for including calibration-time measurements in Figure 14. It also honestly discloses in Figure 12 that the representative-based policies do not always select the optimal waveform. The main weaknesses are that the headline median-improvement claim is not anchored to the deployed policy assignments, and the QEC-threshold conclusion is based on the minimum rather than the typical error rate.

major comments (3)
  1. [Section V-B and Abstract] The abstract states an optimized median error of 0.006, while Section V-B states the median is reduced to 4.4e-3; these numbers are inconsistent and should be reconciled. More importantly, the Section V-B claim that the median is reduced to 4.4e-3, representing a 1.84x improvement over IBM's default pulse configuration, is not accompanied by the measurement protocol: the reader is not told which qubit pairs were included, whether the calibrated median was computed under the actual policy assignments or under the individually optimized waveforms used to construct Figure 12, or how the default-window comparison was controlled for drift. Please specify the population, the deployed waveform assignment, and the exact comparison that produced the 1.84x factor.
  2. [Section V-B (QEC threshold claim)] The statement that the quantum error correction code has entered the region where errors are suppressed relies on the minimum achieved error of 1.3e-3 being below the 3e-3 threshold from reference [4]. A single pair below threshold does not support a claim that the code operates below threshold; the relevant quantity for a threshold argument is the typical or worst-case physical error rate of the gates used by the code, and the reported median of 4.4e-3 is above 3e-3. Additionally, the applicability of the specific threshold value from [4] to IRB-measured ECR error rates on this hardware is not justified. The threshold claim should be removed or heavily qualified.
  3. [Section IV-B2, IV-B3, and Figure 12] The protocol's generalization assumption—that a waveform optimized on a representative pair remains optimal for other pairs in the same cluster or heavy-hex unit-cell position—is violated on a nontrivial fraction of the tested pairs: Figure 12a shows Brute-force Clustering missing the optimal waveform on about 5 of 21 pairs, and Figure 12b shows Topology-oriented Representative missing it on about 2 of 21 pairs. This contradicts the Section V-B statement that the fine-tuned protocol 'can achieve almost the optimal error rate on all qubit pairs.' Please quantify the fidelity penalty from these misassignments and state explicitly whether the headline median error and device-level metrics include these penalties.
minor comments (7)
  1. [Abstract and Section V-B] The word 'medium' is used where 'median' is meant (Abstract and Section V-B); the abstract also contains the typo 'calibraton' and 'server' should be 'serve.'
  2. [Abstract vs Section V-B] The abstract reports a minimum gate error of 0.001, while Section V-B reports a minimum of 1.3e-3; these should be made consistent.
  3. [Section V-B] The phrase 'the total pulse duration is reduced by a factor of 1.26' is ambiguous: it could mean duration becomes 1/1.26 of the original or becomes 1.26 times the original; please clarify.
  4. [Section II-A] The sentence 'However, QPT's bad scalability and it's not applicable to larger systems' is grammatically incomplete; it should be rephrased.
  5. [Figure 13] The normalization used in Figure 13 is not fully defined; the text explains the optimal calibration cost but does not specify how 'optimal' values are determined for gate error and gate duration, nor how the normalized sums are computed.
  6. [Section IV-C] The description 'all single paths with a length of one are selected from the coupling map' is unclear and should be rephrased to 'all edges of the coupling graph are selected' if that is the intended meaning.
  7. [Section I (Contributions)] The claim of 'the first large-scale implementation of multi-derivative DRAG and direct CR operations on real quantum machines' is strong; since reference [24] reports experimental results for multi-derivative DRAG, the novelty claim should be qualified to avoid overstatement.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: the paper's headline improvements are measured benchmarks, and the policy evaluation uses independently measured per-pair optima.

full rationale

The paper's central claims are field measurements on real hardware: gate-error medians, quantum volume and EPLG in Table I, and application-level fidelities in Table II. These are not derived from fitted parameters or from the policies themselves. The policy evaluation in Section V-B is particularly important: for the 21 selected qubit pairs, the paper states it performed 'a comprehensive calibration of three waveforms on each qubit pair, beyond the standard calibration according to each policy,' and Figure 12 compares each policy's selection against the independently measured best waveform. Thus the reported policy-vs-optimal comparison is not forced by construction. The only author-overlapping citation is [24] (multi-derivative DRAG), which supplies the pulse-shaping formula in Eq. (2) and the detuning-dependent guidance used in Section IV-B4. That result is a published external physical result, and the present paper independently tests multi-derivative DRAG on IBM hardware (Figure 12, Table I), so the citation is not a load-bearing self-citation that makes the derivation circular. The internal inconsistencies noted by the skeptic — the abstract median error 0.006 vs. the body median 4.4e-3, and the generalization misses of 5/21 or 2/21 pairs in Figure 12 — are empirical and presentational concerns, not circularity, because they do not amount to a fitted parameter being relabeled as a prediction or to a definitional identification of input and output. No circular step is established.

Assumptions & free parameters 4 free parameters · 4 assumptions · 0 invented entities

The central quantitative claims rest on empirical measurements, but the policy assumptions above are load-bearing. The paper itself provides evidence that representative generalization is imperfect and that parallel calibration is limited by hardware.

free parameters (4)
  • Cluster size n for Brute-force Clustering = 3, 5, 7
    Number of groups is a hand-picked hyperparameter; the paper notes fewer groups speed up calibration, more groups improve accuracy, and the sweet spot is unknown.
  • Calibration error acceptance thresholds = 0.015 MHz initial, relaxed to 0.3 MHz
    Thresholds for accepting calibrated error terms are chosen operationally, not derived; after four failed rounds the threshold is raised, loosening the guarantee for some pairs.
  • Calibration subgraph edge limit = 10 edges, with subgraphs over 20 edges split
    The maximum number of simultaneous custom-pulse calibrations is set by observed hardware failures, not by a model.
  • Minimum graph distance for parallel calibration = 2
    Rule chosen to avoid interference between concurrently calibrated edges; not proven optimal.
assumptions (4)
  • domain assumption The cross-resonance effective Hamiltonian in Eq. (1) and Eq. (3) fully captures the dynamics relevant to ECR calibration.
    Inherited from prior CR calibration literature; if omitted Hamiltonian terms matter, per-pair profiling on these features may not yield the optimal waveform.
  • ad hoc to paper Waveforms optimized on representative qubit pairs remain optimal for all pairs in the same cluster or same heavy-hex position.
    Central to Brute-force Clustering and Topology-oriented policies (Section IV-B2, IV-B3); Figure 12 shows it fails for 5 of 21 and 2 of 21 pairs.
  • domain assumption Calibrating edges at graph distance at least two prevents mutual interference and allows simultaneous calibration.
    Section IV-C; the paper itself revises this with a hardware limit of 10 to 20 edges per subgraph due to observed errors.
  • ad hoc to paper The QEC error threshold of 3e-3 from reference [4] applies to the IRB-measured two-qubit gate error rates on this hardware.
    Used in Section V-B to claim error rates below threshold; reference [4] is a heavy-hex QEC comparison, not the same calibration and drift conditions, and only a minimum error rate is below it.

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Cite this review

Pith. "Pith review of Leveraging Hardware Power through Optimal Pulse Profiling for Each Qubit Pair." pith.science (2026). https://pith.science/paper/K4NIDJGC

@misc{pith2026241119308,
  author       = {Pith},
  title        = {Pith review of: Leveraging Hardware Power through Optimal Pulse Profiling for Each Qubit Pair},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/K4NIDJGC}},
  note         = {Machine review of arXiv:2411.19308}
}
read the original abstract

In the scaling development of quantum computers, the calibration process emerges as a critical challenge. Existing calibration methods, utilizing the same pulse waveform for two-qubit gates across the device, overlook hardware differences among physical qubits and lack efficient parallel calibration. In this paper, we enlarge the pulse candidates for two-qubit gates to three pulse waveforms, and introduce a fine-grained calibration protocol. In the calibration protocol, three policies are proposed to profile each qubit pair with its optimal pulse waveform. Afterwards, calibration subgraphs are introduced to enable parallel calibraton through identifying compatible calibration operations. The protocol is validated on real machine with up to 127 qubits. Real-machine experiments demonstrates a minimum gate error of 0.001 with a median error of 0.006 which is 1.84x reduction compared to default pulse waveform provided by IBM. On device level, a double fold increase in quantum volume as well as 2.3x reduction in error per layered gate are achieved. The proposed protocol leverages the potential current hardware and could server as an important step toward fault-tolerant quantum computing.

Figures

Figures reproduced from arXiv: 2411.19308 by the authors.

Figure 1
Figure 1. Overview of the proposed hardware-aware calibration [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. (a) Calibration circuit for Z phase for the direct CR. [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Enlargement of candidate waveform. Three distinct wave￾forms are developed, each capable of implementing the same basis two-qubit gate on current quantum hardware. These waveforms offer trade-offs among gate fidelity, calibration cost, and gate duration, providing flexibility in optimizing quantum operations based on system constraints. Optimal pulse profiling. In this step, multiple policies are employed, aiming at… view at source ↗
Figures from the paper (13 more)
Figure 3
Figure 3. Figure 3: Overview of the proposed calibration protocol design. With enlarged pulse candidates for ECR gate, optimal waveform [PITH_FULL_IMAGE:figures/full_fig_p005_3.png]
Figure 6
Figure 6. Figure 6: Consequently, applying multi-derivative DRAG may [PITH_FULL_IMAGE:figures/full_fig_p005_6.png]
Figure 6
Figure 6. Figure 6: Top: Relationship between remaining transition er [PITH_FULL_IMAGE:figures/full_fig_p006_6.png]
Figure 4
Figure 4. Figure 4: Examples of the CR pulse: the default pulse shape for [PITH_FULL_IMAGE:figures/full_fig_p006_4.png]
Figure 5
Figure 5. Figure 5: Fidelity, calibration cost, and duration trade-off among [PITH_FULL_IMAGE:figures/full_fig_p006_5.png]
Figure 7
Figure 7. Figure 7: Clustering results for various quantum devices [PITH_FULL_IMAGE:figures/full_fig_p007_7.png]
Figure 8
Figure 8. Figure 8: Repetitive pattern of the heavy-hex lattice, colors [PITH_FULL_IMAGE:figures/full_fig_p008_8.png]
Figure 9
Figure 9. Figure 9: Longitudinal relaxation (T1) and transverse relaxation [PITH_FULL_IMAGE:figures/full_fig_p008_9.png]
Figure 10
Figure 10. Figure 10: Calibration target: remove unwanted interactions from [PITH_FULL_IMAGE:figures/full_fig_p009_10.png]
Figure 11
Figure 11. Figure 11: Dividing a heavy-hex coupling graph into five cali [PITH_FULL_IMAGE:figures/full_fig_p009_11.png]
Figure 12
Figure 12. Figure 12: Performance benchmarking of various waveform [PITH_FULL_IMAGE:figures/full_fig_p009_12.png]
Figure 13
Figure 13. Figure 13: The sum of the gate error rate, calibration cost, and [PITH_FULL_IMAGE:figures/full_fig_p010_13.png]
Figure 14
Figure 14. Figure 14: Calibration time comparison among sequential cali [PITH_FULL_IMAGE:figures/full_fig_p011_14.png]

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