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REVIEW 3 major objections 7 minor 67 references

Vertically Integrated Dual-memtransistor Enabled Reconfigurable Heterosynaptic Sensorimotor Networks and In-memory Neuromorphic Computing

T0 review · 3 major / 7 minor · reviewed 2026-08-11 · deepseek-v4-flash

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Pith's one-line read A single vertically stacked MoS2/In2Se3 transistor can act as two coupled synapses and a Boolean logic gate, the paper argues.

desk verdict The device work is real and the vertical dual-memtransistor architecture is new, but the headline learning accuracies come from idealized crossbar simulations, not from a fabricated array. read the letter →

arxiv 2412.10757 v1 pith:E444M4JV submitted 2024-12-14 physics.app-ph

Srilagna Sahoo , Abin Varghese , Aniket Sadashiva , Mayank Goyal , Jayatika Sakhuja , Debanjan Bhowmik , Saurabh Lodha This is my paper · ORCID
classification physics.app-ph
keywords 2DmaterialsvanderWaalsheterostructureferroelectricsemiconductorMoS2/In2Se3memtransistorheterosynapticplasticityin-memoryneuromorphiccomputingreconfigurableBooleanlogic
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper claims that a single vertically stacked transistor, the VSFET, built from a MoS2 channel on top of a ferroelectric-semiconductor In2Se3 channel on hBN, can serve as two coupled synapse devices accessed by one gate. The authors report that gate-controlled ferroelectric polarization of In2Se3 gives the MoS2 channel memtransistor behavior suitable for homosynaptic plasticity, with measured potentiation and depression nonlinearities of $\alpha_p = 1.74$ and $\alpha_d = -0.07$, and that this behavior yields 90.06% test accuracy in a simulated MNIST classifier after five epochs and 96.2% accuracy in a spiking network on Fisher's iris after two epochs. They further report that simultaneously measuring both channels realizes heterosynaptic cooperation and competition, which they use to mimic the gill-withdrawal reflex sensitization and habituation of Aplysia, and that the same device can be reconfigured as NOT and NOR Boolean gates. If correct, a single area-efficient device could serve as memory, two coupled synapses, and logic, a building block for in-memory neuromorphic computing.

What carries the argument

The load-bearing object is the vertically stratified field-effect transistor (VSFET): a bottom Au gate, an hBN dielectric, a thick n-type In2Se3 ferroelectric semiconductor channel, and a thin n-type MoS2 channel stacked on top, with source/drain contacts on both layers so each layer can be read as an independent transistor while sharing one gate. The out-of-plane ferroelectric polarization of In2Se3 is what stores memory: sweeping the gate beyond the coercive field flips the polarization, and the bound charge at the In2Se3/MoS2 interface modulates the MoS2 channel conductance, producing clockwise hysteresis whose memory window grows with sweep range. The in-plane polarization of the same In2Se3 layer modulates the MoS2 output conductance through Schottky-barrier changes at the contacts, producing pinched resistive hysteresis loops at zero gate bias. Because both channels share the gate, one gate pulse updates two coupled conductances at once; that shared-gate coupling is the mechanism behind the heterosynaptic cooperation and competition, and the same stack is reconfigured as a NOT or NOR gate by choosing which terminals serve as inputs and reading the net source current as the output.

What would settle it

Fabricate a small crossbar array of MoS2/In2Se3 VSFETs, measure the conductance update of every cell across repeated potentiation/depression cycles, and run the same MNIST and iris simulations using the measured array-level nonlinearity and variation; if the 90.06% and 96.2% accuracies collapse or fail to reproduce, the single-device claims stand but the array-level neuromorphic claim falls.

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Extended reading notes

Core claim

The central claim is that stacking a non-ferroelectric 2D semiconductor (MoS2) on a ferroelectric 2D semiconductor (In2Se3) creates two electrostatically coupled memtransistors within one vertical footprint, and that this coupling can be harnessed for both synaptic and logic functions. The out-of-plane ferroelectric polarization of In2Se3 modulates the MoS2 channel conductance, producing the gate-controlled hysteresis that underlies homosynaptic plasticity, while the in-plane polarization of the same In2Se3 layer produces pinched resistive output hysteresis at zero gate bias. Because both channel layers share a single gate, the two synapses can be measured simultaneously and show cooperative or competitive plasticity depending on the drain biases, and the same device can be reconfigured as a NOT or NOR gate by choosing which terminals are inputs.

Load-bearing premise

The simulated neural-network accuracies assume that a crossbar array of VSFETs will behave exactly like the single measured device, with no device-to-device variation and ideal interconnects, and no array was fabricated to test this.

Editorial extensions

If this is right

  • A single VSFET cell could replace two separate synapse devices in a crossbar array, roughly halving the area per synapse while keeping both conductances coupled.
  • The measured potentiation and depression nonlinearity, with $\alpha_p - \alpha_d = 1.81$, is low enough that a five-epoch, one-bit-update multilayer perceptron reaches 90.06% on MNIST, so the device offers a route to simple peripheral circuits.
  • The simultaneously read two channels support cooperative and competitive plasticity in one device, which could help balance and refine synaptic weights during learning.
  • The same device can switch between synaptic memory and NOT/NOR logic, enabling a logic-in-memory architecture without extra area.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Beyond the paper, if the single-device behavior survives in an array, the vertical stacking could push synapse density beyond planar designs because two memtransistors occupy one footprint; a fabricated crossbar would be the natural test.
  • The shared-gate coupling means one input pulse updates two weights simultaneously, which could enable training schemes where correlated synapses are updated together rather than independently.
  • The zero-gate-bias resistive switching from in-plane polarization suggests the VSFET could also be read as a two-terminal memory cell when the gate is idle, expanding its role beyond synaptic emulation.
  • Because the measured learning accuracies are simulation-based, a near-term testable extension is to build a small VSFET crossbar and measure classification accuracy under real device-to-device variation.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 7 minor

Summary. The paper reports a vertically stacked MoS2/In2Se3 field-effect transistor (VSFET) in which a top MoS2 channel and a bottom ferroelectric-semiconductor In2Se3 channel share a common gate and are electrostatically coupled. The authors demonstrate hysteretic transfer and output characteristics, attribute the hysteresis to coupled out-of-plane and in-plane ferroelectric polarization of In2Se3, and use the gate-controlled MoS2 channel to emulate homosynaptic plasticity (potentiation/depression and STDP). From measured P/D and STDP curves they simulate supervised MNIST and unsupervised iris classification accuracies of 90.06% and 96.2%, respectively. Simultaneous measurements of both channels are used to demonstrate heterosynaptic cooperation and competition, which are mapped onto a conceptual Aplysia gill-withdrawal model. Finally, the device is reconfigured to implement NOT and NOR logic gates.

Significance. If the claims are properly scoped, the VSFET is a useful building block for in-memory neuromorphic computing: it is area-efficient, combines two coupled synapses in a vertical stack, shows both homosynaptic and heterosynaptic plasticity, and can be reconfigured as logic gates. The strength of the work lies in the direct device-level measurements, the inclusion of C-MoS2 and C-In2Se3 control devices that support the ferroelectric-coupling attribution, the demonstration of simultaneous access to two coupled channels, and the use of measured P/D and STDP data as inputs to network simulations rather than purely abstract model parameters. The main weakness is that the headline 'on-chip learning' accuracies are not hardware results but single-device-to-simulation extrapolations, so the significance depends on whether array-level variability is small or the claims are appropriately qualified.

major comments (3)
  1. [Homosynaptic Plasticity and Neuromorphic In-Memory Computing, Figure 4] The abstract and main text claim 'high accuracy supervised and unsupervised on-chip learning' (90.06% MNIST, 96.2% iris), but these numbers are not obtained from a fabricated crossbar array; they are simulations that use the measured P/D and STDP curves from a single device. The manuscript itself states that 'the P/D parameters extracted from Figure 4b were used to model the hardware implementation of a NN circuit utilizing MoS2/In2Se3 vdW VSFET arrays in crossbar architecture,' and no array-level measurements or multi-device statistics are reported. The learning-accuracy claims therefore rest on the untested assumption that the single measured device is representative of an entire array with no device-to-device variation, interconnect resistance, or write noise. To support the central claim, the authors should either present array or statistical-ensemble measurements, or explicitly re-label these results as simulations and qualify the 'on-chip' language in the abstract.
  2. [Homosynaptic Plasticity and Neuromorphic In-Memory Computing, Table 2 and Figure 4d] The relationship between the reported test accuracies is inconsistent and unexplained. Figure 4d reports 90.06% for 'on-chip learning' using the incremental-amplitude pulse scheme, while Table 2 lists 97.21% for the same scheme under 'on-chip inference.' If the Table 2 numbers refer to inference after offline training with ideal weights mapped to the device, that should be stated; if they refer to on-chip training, the discrepancy with Figure 4d is substantial and needs a reason. Without clarification, the central accuracy numbers cannot be interpreted.
  3. [Homosynaptic Plasticity and Neuromorphic In-Memory Computing, Figure 4f] The 96.2% unsupervised SNN accuracy on Fisher's iris is presented without the network architecture, neuron model, input encoding, or spike-timing simulation details; the reader is only referred to prior work [44]. Given that the measured STDP time constants are approximately 113 ms and 337 ms, the SNN simulation must also specify the mapping between physical time and simulation time. Without these details, the unsupervised learning result is not reproducible.
minor comments (7)
  1. [Abstract] The abstract describes the device as showing 'low nonlinearity' but the reported potentiation nonlinearity factor is alpha_p = 1.74; please state the numerical values or clarify the comparison baseline.
  2. [Figure 4d caption] The caption refers to 'on-chip learning accuracy numbers' but these numbers come from simulations. Please use 'simulated' or 'modeled' in the caption and throughout the text.
  3. [Supporting Information 7] The mapping from the fitted parameters A_P and A_D to the nonlinearity factors alpha_p and alpha_d is not shown explicitly; please provide the full formula or a reference to the exact NeuroSim documentation page.
  4. [Energy per spike, Homosynaptic Plasticity section] The equation E_perspike = I_PSC * V_D * t_spike uses the drain-side voltage, but the presynaptic spike is applied at the gate; please justify why gate leakage current is negligible and clarify why the drain-side energy is the relevant metric.
  5. [Biomimetic Heterosynaptic Interactions in Sea Mollusk] The text says 'the HT-MoS2 and HB-MoS2 synapses' but the bottom channel is In2Se3, not MoS2; this should read 'HT-MoS2 and HB-In2Se3.'
  6. [Table 1, Conclusion] In the comparison table, 'Fisher's Irish' should be 'Fisher's Iris.'
  7. [References [45-47]] References [45-47] are URLs of Wikimedia Commons images; these are not standard citations for a scientific journal and should be replaced with proper data or literature citations.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the learning accuracies are network simulations fed by measured P/D and STDP curves, not predictions forced by the model's own definitions.

full rationale

The paper's derivation chain is a sequence of measurements followed by simulations and biological analogies. Measured transfer/output hysteresis and PFM establish ferroelectric coupling; measured P/D responses (Fig. 4b) and STDP curves (Fig. 4e) are used as weight-update characteristics in standard backpropagation and spiking-neural-network frameworks (refs 39, 40) to obtain the reported MNIST and Fisher Iris accuracies. The accuracy numbers are conditional simulations of an ideal crossbar, not a hidden return of the fitting inputs: the same measured curves could feed many network models and yield different accuracies, and the network output is not used to define the device parameters. The references to Kaushik et al. and Yadav et al. are self-citations by co-author Bhowmik, but they are invoked only for simulator/training-algorithm details and are not the source of the device's measured nonlinearity or STDP constants. The heterosynaptic cooperation/competition and Aplysia mimicry are interpretive labels applied to simultaneous measurements of two coupled channels sharing a gate; they involve no quasi-theoretical prediction that reduces to its own inputs. The main weakness is external validity: no crossbar array was fabricated, and the network accuracy extrapolates from one device, an extrapolation/validation gap rather than circular reasoning. Overall score 0.

Assumptions & free parameters 4 free parameters · 5 assumptions · 0 invented entities

The central claims rest on four fitted parameters (potentiation and depression nonlinearity factors, two STDP time constants) and on domain assumptions that include extrapolating a single device to an array and equating two stacked channels with two biological synapses. No new physical entities are introduced.

free parameters (4)
  • Potentiation nonlinearity factor alpha_p = 1.74
    Fitted to the measured potentiation curve via the Neurosim mapping (SI Section 7); used in the ANN simulation.
  • Depression nonlinearity factor alpha_d = -0.07
    Fitted to the measured depression curve via the Neurosim mapping; used in the ANN simulation.
  • STDP potentiation time constant tau+ = 113 ms
    Exponential fit to measured STDP data for positive Delta t, reported in the STDP section.
  • STDP depression time constant tau- = 337 ms
    Exponential fit to measured STDP data for negative Delta t.
assumptions (5)
  • domain assumption Hysteresis in HT-MoS2 originates from ferroelectric polarization of In2Se3 rather than charge trapping or interface defects.
    Used in the Device Physics section to explain MW expansion with VGmax; supported by the C-MoS2 control and PFM, but trapping is not explicitly excluded.
  • domain assumption A crossbar array of VSFETs will reproduce the single-device P/D and transfer behavior with negligible device-to-device variation.
    Invoked when P/D parameters from one device are used to model MNIST accuracy in Figure 4c-d; no array was fabricated.
  • domain assumption Reading the two stacked channels simultaneously represents heterosynaptic plasticity between two synapses.
    The biological mapping in Figures 5-6 treats the two channels as two synapses; the shared gate is a simplification relative to biology.
  • domain assumption alpha-In2Se3 retains its ferroelectric and correlated IP-OOP polarization when covered by MoS2.
    PFM is performed on In2Se3 flakes (Figure S1), and device behavior is consistent, but no direct PFM on the final stacked device is shown.
  • standard math Standard backpropagation and STDP learning rules apply to the simulated networks.
    The ANN and SNN simulations rely on textbook learning algorithms; this is not a source of circularity.

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Cite this review

Pith. "Pith review of Vertically Integrated Dual-memtransistor Enabled Reconfigurable Heterosynaptic Sensorimotor Networks and In-memory Neuromorphic Computing." pith.science (2026). https://pith.science/paper/E444M4JV

@misc{pith2026241210757,
  author       = {Pith},
  title        = {Pith review of: Vertically Integrated Dual-memtransistor Enabled Reconfigurable Heterosynaptic Sensorimotor Networks and In-memory Neuromorphic Computing},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/E444M4JV}},
  note         = {Machine review of arXiv:2412.10757}
}
abstract

Neuromorphic in-memory computing requires area-efficient architecture for seamless and low latency parallel processing of large volumes of data. Here, we report a compact, vertically integrated/stratified field-effect transistor (VSFET) consisting of a 2D non-ferroelectric MoS$_2$ FET channel stacked on a 2D ferroelectric In$_2$Se$_3$ FET channel. Electrostatic coupling between the ferroelectric and non-ferroelectric semiconducting channels results in hysteretic transfer and output characteristics of both FETs. The gate-controlled MoS$_2$ memtransistor is shown to emulate homosynaptic plasticity behavior with low nonlinearity, low epoch, and high accuracy supervised (ANN - artificial neural network) and unsupervised (SNN - spiking neural network) on-chip learning. Further, simultaneous measurements of the MoS$_2$ and In$_2$Se$_3$ transistor synapses help realize complex heterosynaptic cooperation and competition behaviors. These are shown to mimic advanced sensorimotor neural network-controlled gill withdrawal reflex sensitization and habituation of a sea mollusk (Aplysia) with ultra-low power consumption. Finally, we show logic reconfigurability of the VSFET to realize Boolean gates thereby adding significant design flexibility for advanced computing technologies.

Figures

Figures reproduced from arXiv: 2412.10757 by the authors.

Figure 1
Figure 1. Device structure and Raman spectra. (a) 3D schematic of MoS [PITH_FULL_IMAGE:figures/full_fig_p006_1.png] view at source ↗
Figure 2
Figure 2. DC electrical characteristics of VSFET. (a) Comparison of transfer characteristics [PITH_FULL_IMAGE:figures/full_fig_p009_2.png] view at source ↗
Figure 3
Figure 3. Device physics for |VGmax| dependent ID - VG hysteresis in HT-MoS2 FET. (a) The transfer curve of HT-MoS2 FET on the left has four marked points, 1, 2, 3, and 4, representing four operating points of the device in a clockwise direction for |VGmax| = 10 V. Energy band diagrams for (b) point 2 and (c) point 4 illustrate the change in electrostatics, spatial electric field, and charge distribution corresponding to a ch… view at source ↗
Figures from the paper (4 more)
Figure 4
Figure 4. Figure 4: Neuromorphic in-memory computing using HT-MoS [PITH_FULL_IMAGE:figures/full_fig_p015_4.png]
Figure 5
Figure 5. Figure 5: Heterosynaptic interactions utilizing VSFET. (a) Schematics showing two inter [PITH_FULL_IMAGE:figures/full_fig_p017_5.png]
Figure 6
Figure 6. Figure 6: Biomimetic heterosynaptic response and defensive learning behavior of sea mol [PITH_FULL_IMAGE:figures/full_fig_p019_6.png]
Figure 7
Figure 7. Figure 7: Boolean logic gates using VSFET. (a) 2D device cross-section biasing schematic [PITH_FULL_IMAGE:figures/full_fig_p020_7.png]

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Pith tools

Reviewed August 11, 2026 · model on record in the stance chip above.