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Paper Citation Record · LEDGER

A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs

As of 18 August 2026, this Paper Citation Record lists 25 of 25 outbound references and 0 inbound Pith citation observations for arXiv:2412.19869.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2412.19869 v1

Coverage vector

measured 25 of 25 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-11T00:18:07.324110Z

measured 25 of 25 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-18T06:34:40.430872+00:00

measured 0 of 0 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: cited_works

Reference resolution

25 of 25 outbound references displayed

  • verified exact1
  • verified fuzzy22
  • unresolved2
  • parse uncertain0
  • malformed identifier0
  • metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation 49bf387f-0ae6-4864-b598-3983022b1f6f · outbound

This paper cites Equivalent-accuracy accelerated neural-network training using analogue memory,.

A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs Equivalent-accuracy accelerated neural-network training using analogue memory,

Reference 1

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verified fuzzy
raw_fallback, observed 2026-08-11T00:18:07.651496Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

source=pdf_text observed=2026-08-11T00:18:07.226347Z digest=sha256:6d3d532d7988d2fa123e936557451c23fe27016db8ec87337df125219928ecf0

Observation c9e69729-60a5-4f39-953b-54ed8c7a43f3 · outbound

This paper cites A compute-in-memory chip based on resistive random-access memory,.

A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs A compute-in-memory chip based on resistive random-access memory,

Reference 2

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unresolved
no resolver link, observed 2026-08-11T00:18:07.231069Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-11T00:18:07.231069Z digest=sha256:9b6105d0831899dde0cbeb8f16648ff050a2399fda7f3967339d32f3635d5f01

Observation 458784b2-9502-4573-afee-2912bb4698cd · outbound

This paper cites Hardware implementation of memristor-based artificial neural networks,.

A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs Hardware implementation of memristor-based artificial neural networks,

Reference 3

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verified fuzzy
raw_fallback, observed 2026-08-11T00:18:07.631838Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

source=pdf_text observed=2026-08-11T00:18:07.235416Z digest=sha256:7ecd4f7a8d50f31d684163926b256ab1d44f7d428efbfe63cfc3e70b5ec496ec

Observation d250510e-b76c-41aa-8d73-9ef05f3bc39b · outbound

This paper cites Towards a formally verified hardware root-of-trust for data-oblivious computing,.

A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs Towards a formally verified hardware root-of-trust for data-oblivious computing,

Reference 4

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verified fuzzy
raw_fallback, observed 2026-08-11T00:18:07.620036Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

source=pdf_text observed=2026-08-11T00:18:07.239467Z digest=sha256:2abcd67eec36d8218c6c4d41b31a092933af3b235ecbbcdf4dba88f00c591569

Observation 095ad482-37f2-4aed-88a2-28585fc17bdd · outbound

This paper cites Design guidelines of rram based neural-processing-unit: A joint device- circuit-algorithm analysis,.

A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs Design guidelines of rram based neural-processing-unit: A joint device- circuit-algorithm analysis,

Reference 5

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verified fuzzy
raw_fallback, observed 2026-08-11T00:18:07.608881Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

source=pdf_text observed=2026-08-11T00:18:07.243858Z digest=sha256:7ff0b237a18d3162398b18031fe6c8cc12733a7b73f7b86d672fc8e8522e72e0

Observation 7e9c3af8-4be1-4724-88ea-71d88a33b968 · outbound

This paper cites Fpcim: A fully- parallel robust reram cim processor for edge ai devices,.

A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs Fpcim: A fully- parallel robust reram cim processor for edge ai devices,

Reference 6

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verified fuzzy
raw_fallback, observed 2026-08-11T00:18:07.597593Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

source=pdf_text observed=2026-08-11T00:18:07.248157Z digest=sha256:9ecee4a7ba5bccd30dffaf2d908ea49064aeb5213c4565b2bd839f7babc34805

Observation 143fdcc9-ed82-4fa7-84d9-410d1f10ec83 · outbound

This paper cites Prime: A novel processing-in-memory architecture for neural network computation in reram-based main memory,.

A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs Prime: A novel processing-in-memory architecture for neural network computation in reram-based main memory,

Reference 7

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verified fuzzy
raw_fallback, observed 2026-08-11T00:18:07.586223Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

source=pdf_text observed=2026-08-11T00:18:07.253059Z digest=sha256:52b13a55de8b1aa16320c98beff597b3c641942acd662feb6448e38f6963291e

Observation 29b621c3-c936-4122-8191-78822c44a8e7 · outbound

This paper cites Neurosim+: An integrated device- to-algorithm framework for benchmarking synaptic devices and array architectures,.

A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs Neurosim+: An integrated device- to-algorithm framework for benchmarking synaptic devices and array architectures,

Reference 8

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verified fuzzy
raw_fallback, observed 2026-08-11T00:18:07.575353Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

source=pdf_text observed=2026-08-11T00:18:07.256928Z digest=sha256:7a79b2621f61f19427c85f1e2a54500f0cfda4f905956d39ea9c0d7fc5f28dde

Observation 14b6f809-1bf7-4e57-950a-b261501bea1f · outbound

This paper cites Compute-in-memory technologies and architectures for deep learning workloads,.

A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs Compute-in-memory technologies and architectures for deep learning workloads,

Reference 9

Resolution
verified fuzzy
raw_fallback, observed 2026-08-11T00:18:07.564786Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

source=pdf_text observed=2026-08-11T00:18:07.260710Z digest=sha256:436b07153856f8f9c4c926bb8b8467dec25e7845a298dab2ff0d8aa539749451

Observation b4a0f125-388e-49fe-8c68-1d31d70f68c2 · outbound

This paper cites Fully hardware-implemented memristor convolutional neural network,.

A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs Fully hardware-implemented memristor convolutional neural network,

Reference 10

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verified fuzzy
raw_fallback, observed 2026-08-11T00:18:07.553243Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

source=pdf_text observed=2026-08-11T00:18:07.264338Z digest=sha256:c1d901a2ea294cd7e6977d64821fa3d1bf42823e6f2b9184859c04f3f7b492dd

Observation e46d660b-9c4d-4200-9706-7defbb357f7e · outbound

This paper cites Enabling highly-efficient dna sequence mapping via reram-based tcam,.

A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs Enabling highly-efficient dna sequence mapping via reram-based tcam,

Reference 11

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verified fuzzy
raw_fallback, observed 2026-08-11T00:18:07.541585Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

source=pdf_text observed=2026-08-11T00:18:07.268106Z digest=sha256:336a31fda009ed8be8018bd8af532d34d392ccc81b3bcd53b48c2a57e37865e4

Observation ed4bdc5c-ce36-49a1-ad91-1a1afc734da5 · outbound

This paper cites Winner-take-all autoencoders,.

A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs Winner-take-all autoencoders,

Reference 12

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verified fuzzy
raw_fallback, observed 2026-08-11T00:18:07.529741Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

source=pdf_text observed=2026-08-11T00:18:07.271787Z digest=sha256:3a2d9077979e3a37223ccfcc6b00d458e4d29f1d3114fd89777aba06802510c5

Observation e94d084c-5b92-4c41-b46c-1260390cc375 · outbound

This paper cites Thermal agitation of electricity in conductors,.

A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs Thermal agitation of electricity in conductors,

Reference 13

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verified fuzzy
raw_fallback, observed 2026-08-11T00:18:07.518020Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

source=pdf_text observed=2026-08-11T00:18:07.275636Z digest=sha256:c990293116d9ffd6a3e56f48f777f3b728b68ac8ba8086733992cffc4527555b

Observation c62cdd58-0ed4-4220-a491-b12fee5a0793 · outbound

This paper cites Swipe: Enhancing robustness of reram crossbars for in-memory computing,.

A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs Swipe: Enhancing robustness of reram crossbars for in-memory computing,

Reference 14

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verified fuzzy
raw_fallback, observed 2026-08-11T00:18:07.505530Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

source=pdf_text observed=2026-08-11T00:18:07.279295Z digest=sha256:7fc441b3eb42a531a43ca41327288569a5f4e08ae3f8a7a6eb3c52c0c974018c

Observation a8e59adc-4ffb-4993-adfd-93d3e540c14d · outbound

This paper cites Mixed-signal computing for deep neural network in- ference,.

A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs Mixed-signal computing for deep neural network in- ference,

Reference 15

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verified fuzzy
raw_fallback, observed 2026-08-11T00:18:07.492398Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

source=pdf_text observed=2026-08-11T00:18:07.283064Z digest=sha256:fd1935752e2fc3df4715dadaa44d09109ac6d919823b5e32c67e20d88b7f2578

Observation e3d5305d-423e-4eba-842d-2a43bd4bf969 · outbound

This paper cites Towards adc-less compute-in- memory accelerators for energy efficient deep learning,.

A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs Towards adc-less compute-in- memory accelerators for energy efficient deep learning,

Reference 16

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verified fuzzy
raw_fallback, observed 2026-08-11T00:18:07.479050Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

source=pdf_text observed=2026-08-11T00:18:07.286999Z digest=sha256:70557f5904e194204dc48d12d0d0909dabc92567f718b99a2fee8c019c33f1e5

Observation 18924650-080d-471d-b52a-c3717f00817a · outbound

This paper cites Analog-to-digital conversion with reconfig- urable function mapping for neural networks activation function accel- eration,.

A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs Analog-to-digital conversion with reconfig- urable function mapping for neural networks activation function accel- eration,

Reference 17

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verified fuzzy
raw_fallback, observed 2026-08-11T00:18:07.465210Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

source=pdf_text observed=2026-08-11T00:18:07.291032Z digest=sha256:704d2b5fd38790c3bf8fd2e54fe9fc23b4b1f9ada9d5c1c2ba432709519352fb

Observation 99d3d855-9e66-44db-823a-d355151fe77f · outbound

This paper cites an unresolved cited work.

A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs Unresolved cited work

Reference 18

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unresolved
raw_fallback, observed 2026-08-11T00:18:07.452743Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

source=pdf_text observed=2026-08-11T00:18:07.295092Z digest=sha256:61a034a55a9562317bf9f2ba62724a3c58f0859596b91b9a7f725cbad1b1a0da

Observation 371ed83a-2d60-481e-90fb-23b89aad3c2e · outbound

This paper cites 574–579, IEEE, 2018.

A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs 574–579, IEEE, 2018

Reference 19

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raw_fallback, observed 2026-08-11T00:18:07.441609Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

source=pdf_text observed=2026-08-11T00:18:07.299110Z digest=sha256:4484ed1027c541ce2597b888b82330f33efcef1cfe019b778b6cab7cd06d48eb

Observation c0d68539-991b-41c9-8b8d-e3dafb27ffc7 · outbound

This paper cites Improving robustness of reram-based spiking neural network accelerator with stochastic spike- timing-dependent-plasticity,.

A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs Improving robustness of reram-based spiking neural network accelerator with stochastic spike- timing-dependent-plasticity,

Reference 20

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verified fuzzy
raw_fallback, observed 2026-08-11T00:18:07.429118Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

source=pdf_text observed=2026-08-11T00:18:07.303057Z digest=sha256:a497424cf9ffab662c5d9804ee7563793ca5c5367d0eb33f4203923c0215cb3f

Observation 8c0152e4-5819-4c81-8e36-c3b69c7090b8 · outbound

This paper cites Regularized Binary Network Training.

A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs Regularized Binary Network Training

Reference 21

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local_arxiv, observed 2026-08-11T00:18:07.362633Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

source=pdf_text observed=2026-08-11T00:18:07.307750Z digest=sha256:64f9d293e484535f256982d0889b7f8224d53c89eceed2d543adcf0366d8cdc1

Observation 69693d08-eb77-4898-ac46-f5077cd7e8a9 · outbound

This paper cites Rram-based spiking nonvolatile computing-in-memory processing engine with precision- configurable in situ nonlinear activation,.

A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs Rram-based spiking nonvolatile computing-in-memory processing engine with precision- configurable in situ nonlinear activation,

Reference 22

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verified fuzzy
raw_fallback, observed 2026-08-11T00:18:07.415988Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

source=pdf_text observed=2026-08-11T00:18:07.312511Z digest=sha256:1c37fbfbfac7932eacefca92c0d3d95b5a71458165e249aedd2a731c8616af11

Observation 13c48343-3bc4-4646-acb4-f25e7dc8dd54 · outbound

This paper cites Stochastic phase-change neurons,.

A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs Stochastic phase-change neurons,

Reference 23

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verified fuzzy
raw_fallback, observed 2026-08-11T00:18:07.402854Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

source=pdf_text observed=2026-08-11T00:18:07.316348Z digest=sha256:82e712d7f78fea3b47ea17063cac3c15cdbe1914f5ffc72d5e4e036e99055396

Observation 3964b48c-890f-4361-adab-ffc5081c7716 · outbound

This paper cites Simple statistical gradient-following algorithms for con- nectionist reinforcement learning,.

A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs Simple statistical gradient-following algorithms for con- nectionist reinforcement learning,

Reference 24

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verified fuzzy
raw_fallback, observed 2026-08-11T00:18:07.388762Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

source=pdf_text observed=2026-08-11T00:18:07.320182Z digest=sha256:599cbeef534331fe135f9358f0bd7ec7c414ca825961028806a2c4ec6258ac29

Observation b46220b1-c15c-48f5-874b-69e426dd828f · outbound

This paper cites Versatile stochastic dot product circuits based on nonvolatile memories for high perfor- mance neurocomputing and neurooptimization,.

A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs Versatile stochastic dot product circuits based on nonvolatile memories for high perfor- mance neurocomputing and neurooptimization,

Reference 25

Resolution
verified fuzzy
raw_fallback, observed 2026-08-11T00:18:07.376230Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

source=pdf_text observed=2026-08-11T00:18:07.324110Z digest=sha256:25fa1340c769a2b1f51debf05efc694f10f7ad92bc4e9e401e0f820fd8a13137

Pith citing papers

No inbound Pith citation observations are available.