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Next-Gen Computing Systems with Compute Express Link: a Comprehensive Survey

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arxiv 2412.20249 v2 pith:PWK7ABSJ submitted 2024-12-28 cs.DC

Next-Gen Computing Systems with Compute Express Link: a Comprehensive Survey

classification cs.DC
keywords memorysystemscomputinginterconnectionprocessorsdevicesperformanceaccelerators
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved
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Interconnection is crucial for computing systems. However, the current interconnection performance between processors and devices, such as memory devices and accelerators, significantly lags behind their computing performance, severely limiting the overall performance. To address this challenge, Intel proposes Compute Express Link (CXL), an open industry-standard interconnection. With memory semantics, CXL offers low-latency, scalable, and coherent interconnection between processors and devices. This paper introduces recent advances in CXL-based computing systems from single-machine to distributed. In single-machine systems, we classify existing research into two categories: Memory Expansion and Unified Memory. Memory Expansion focus on processors and memory, aims to address memory wall challenge. Unified memory focus on processors and accelerators, aims to enhance collaboration in heterogeneous computing systems. In distributed systems, we present how to build efficient disaggregation systems based on CXL infrastructure, enabling resource pooling and sharing. Finally, we discuss the future research and envision memory-centric computing with CXL.

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Cited by 3 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. From Tensor Buffer to Distributed Memory Hierarchy: A Survey of KV Cache Management for LLM Serving

    cs.DC 2026-06 accept novelty 6.5

    KV-cache serving systems concentrate into five archetypes under a four-axis taxonomy, with ownership explaining residual distributed design variance and seven measurement gaps blocking next steps.

  2. Bridging the Cognitive Gap: A Unified Memory Paradigm for 6G Agentic AI-RAN

    cs.NI 2026-05 conditional novelty 6.0

    Proposal to replace message-passing interfaces in AI-RAN with zero-copy CXL shared memory, organized as reflexive, contextual, and evolutionary cognitive loops.

  3. Bridging the Cognitive Gap: A Unified Memory Paradigm for 6G Agentic AI-RAN

    cs.NI 2026-05 unverdicted novelty 4.0

    A memory-centric architecture is envisioned for 6G networks to create a cognitive continuum where AI agents access multi-timescale state via zero-copy observability instead of message passing.