An Efficient Stochastic Subgradient Method for the Global Placement Problem in Very Large-Scale Integration Circuits

Haijun Yu; Yi-Shuang Yue; Yu-Hong Dai

arxiv: 2412.20425 · v2 · submitted 2024-12-29 · 🧮 math.OC

An Efficient Stochastic Subgradient Method for the Global Placement Problem in Very Large-Scale Integration Circuits

Yi-Shuang Yue , Yu-Hong Dai , Haijun Yu This is my paper

Pith reviewed 2026-05-23 06:32 UTC · model grok-4.3

classification 🧮 math.OC

keywords VLSI placementglobal placementstochastic subgradientReLU penaltywirelength optimizationnonconvex optimizationconvergence proof

0 comments

The pith

Transforming nonoverlapping constraints into ReLU penalties lets stochastic subgradient methods solve VLSI global placement with a convergence guarantee.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper develops a penalty model that converts the nonoverlapping constraints of circuit placement directly into rectified linear functions. This recasts the nonsmooth wirelength objective into a form that mirrors ReLU neural network training, so automatic differentiation can supply subgradients for a stochastic subgradient algorithm. Experiments on GSRC and ISPD2005 benchmarks report lower wirelength together with eliminated overlaps. The authors also supply a convergence proof, presented as the first such guarantee for ReLU-type nonsmooth nonconvex problems. The approach matters because wirelength directly affects signal delay and power in manufactured chips.

Core claim

By converting nonoverlapping constraints into rectified linear penalty functions, the placement problem becomes analogous to ReLU network training; automatic differentiation then yields the subgradient needed for a stochastic subgradient solver whose convergence is proved for the first time on this class of problems, and the method produces lower wirelength with no overlaps on standard benchmarks.

What carries the argument

Rectified linear penalty functions for nonoverlapping constraints, solved via stochastic subgradient iteration with automatic differentiation.

Load-bearing premise

The nonoverlapping constraints can be turned into rectified linear penalties without introducing bias that changes solution quality or requires extra tuning.

What would settle it

On the ISPD2005 circuits the final placements still contain overlaps or the total wirelength fails to improve over the best published results.

read the original abstract

The placement problem in Very Large-Scale Integration (VLSI) circuits is a critical step in chip design. Its primary goal is to optimize the wirelength of circuit components within a confined area while adhering to nonoverlapping constraints. This paper introduces a novel approach that directly optimizes the original nonsmooth wirelength and proposes an innovative penalty model tailored for the global placement problem. Specifically, we transform the nonoverlapping constraints into rectified linear penalty functions, allowing for a more precise formulation of the problem. Notably, we recast the resultant optimization problem into a form analogous to training deep neural network with Rectified Linear Units (ReLU). Leveraging automatic differentiation techniques from deep learning, we efficiently compute the subgradient of the objective function. This facilitates the application of stochastic subgradient methods to solve the model. To enhance the algorithm's performance, several advanced techniques are further introduced, leading to significant improvements in both efficiency and solution quality. Numerical experiments were conducted on Gigascale Systems Research Center (GSRC) benchmark and International Symposium on Physical Design 2005 (ISPD2005) benchmark circuits. The results demonstrate that our proposed model and algorithm achieve significant reductions in wirelength while effectively eliminating overlaps. This highlights the potential of our approach as a transformative advancement for VLSI placement. Furthermore, we establish a rigorous convergence proof for the proposed stochastic subgradient method. To the best of our knowledge, it constitutes the first such result for the ReLU-type nonsmooth and nonconvex optimization problems.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

The paper recasts VLSI placement with ReLU penalties and stochastic subgradients, claiming the first convergence proof for that nonsmooth nonconvex class, but the finite-penalty feasibility claim needs checking.

read the letter

The main takeaway is that this work turns non-overlap constraints into ReLU-style penalties, computes subgradients via automatic differentiation, and runs a stochastic subgradient method with a claimed first convergence result for ReLU-type problems. Experiments on GSRC and ISPD2005 circuits report lower wirelength and effective overlap removal compared to prior approaches. That combination of modeling trick and proof is the concrete new element. The practical side benefits from borrowing DL tooling for efficiency on large instances, and the benchmarks are standard, so the reported gains are at least testable. The proof itself, if it holds without extra assumptions, would be a solid technical step for this problem class. The soft spot sits in the penalty reformulation. Standard ReLU penalties only enforce constraints exactly as the multiplier goes to infinity; for any fixed value the stationary points can retain some overlap or shift the wirelength optimum. The abstract gives no bound on residual violation, no adaptive schedule with guarantee, and no post-processing step whose cost is controlled. If the full paper does not supply one of those, the “effective elimination” on the test cases could be parameter-specific rather than general. The convergence statement is for the penalized problem, so the link back to the original hard-constraint placement still needs explicit justification. This is worth a serious referee. The target reader is someone working on VLSI global placement or on nonsmooth nonconvex methods who wants to see how DL-style tricks transfer and whether the proof closes a gap. The experimental setup and the proof attempt are substantial enough that desk rejection would be premature; a referee can sort the modeling details and verify the novelty claim against existing placement literature. I would send it out for review.

Referee Report

1 major / 1 minor

Summary. The paper proposes transforming the nonoverlapping constraints in VLSI global placement into ReLU penalty functions, recasting the resulting nonsmooth nonconvex problem in a form amenable to stochastic subgradient methods via automatic differentiation (analogous to ReLU network training). It introduces algorithmic enhancements, reports numerical results on GSRC and ISPD2005 benchmarks claiming significant wirelength reductions with effective overlap elimination, and supplies a convergence proof asserted to be the first for ReLU-type nonsmooth nonconvex problems.

Significance. A correct convergence analysis for this class of problems would be a technical contribution to nonsmooth nonconvex optimization. If the penalty formulation produces feasible placements with the reported quality improvements on standard benchmarks, the approach could provide a practical alternative for large-scale placement by importing tools from deep learning.

major comments (1)

[Abstract and model formulation] Abstract and penalty model: the nonoverlapping constraints are replaced by ReLU penalties of the form max(0, overlap) scaled by a finite multiplier. Stationary points of the penalized objective need not be feasible for the original problem; the manuscript provides no a-priori bound on residual overlap, no adaptive multiplier schedule with feasibility guarantee, and no post-processing whose cost is shown to be negligible. This directly affects the central claim that overlaps are 'effectively eliminated' while achieving wirelength reductions.

minor comments (1)

[Abstract] The abstract asserts 'significant reductions in wirelength' without numerical values or baseline comparisons; adding concrete metrics (e.g., percentage improvement over a reference placer) would improve clarity.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the constructive feedback. We address the major comment on the penalty formulation below.

read point-by-point responses

Referee: [Abstract and model formulation] Abstract and penalty model: the nonoverlapping constraints are replaced by ReLU penalties of the form max(0, overlap) scaled by a finite multiplier. Stationary points of the penalized objective need not be feasible for the original problem; the manuscript provides no a-priori bound on residual overlap, no adaptive multiplier schedule with feasibility guarantee, and no post-processing whose cost is shown to be negligible. This directly affects the central claim that overlaps are 'effectively eliminated' while achieving wirelength reductions.

Authors: We agree that a finite penalty multiplier implies stationary points of the penalized problem need not be feasible for the original constrained formulation, and the manuscript provides neither an a priori bound on residual overlap nor an adaptive schedule guaranteeing feasibility. Our numerical results on the GSRC and ISPD2005 benchmarks show that a fixed, sufficiently large multiplier yields placements with negligible overlap in practice, and no post-processing is applied. To address the comment we will revise the manuscript to report quantitative residual-overlap metrics, detail the penalty-parameter selection procedure, and moderate the language in the abstract and conclusions to reflect empirical effectiveness on the tested instances rather than a general feasibility guarantee. revision: yes

Circularity Check

0 steps flagged

No significant circularity; derivation relies on independent modeling choice and external convergence analysis

full rationale

The paper selects a ReLU penalty reformulation of nonoverlap constraints as a modeling decision, recasts the problem by analogy to DNN training, applies automatic differentiation and stochastic subgradient methods, and supplies a convergence proof claimed as novel for this problem class. None of these steps reduce by construction to fitted parameters renamed as predictions, self-citations that bear the central load, or self-definitional equivalences; the experimental results on GSRC/ISPD2005 benchmarks and the mathematical convergence argument remain independent of the target claims.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Abstract-only; no free parameters, axioms, or invented entities are specified in the provided text.

pith-pipeline@v0.9.0 · 5804 in / 907 out tokens · 38135 ms · 2026-05-23T06:32:56.696550+00:00 · methodology

discussion (0)

Lean theorems connected to this paper

Citations machine-checked in the Pith Canon. Every link opens the source theorem in the public Lean library.

IndisputableMonolith/Cost/FunctionalEquation.lean washburn_uniqueness_aczel unclear

?

unclear
Relation between the paper passage and the cited Recognition theorem.

transform the non-overlapping constraints into rectified linear penalty functions... ϕ_{r,t}(x,y) ... ℓ_{xy}=ϕ... min HPWL + γ ℓ_b + γ ℓ_{xy}
IndisputableMonolith/Foundation/BranchSelection.lean branch_selection unclear

?

unclear
Relation between the paper passage and the cited Recognition theorem.

reformulate ... as a deep ReLU neural network with max{⌈log M⌉+1,3} ReLU layers

What do these tags mean?

matches: The paper's claim is directly supported by a theorem in the formal canon.
supports: The theorem supports part of the paper's argument, but the paper may add assumptions or extra steps.
extends: The paper goes beyond the formal theorem; the theorem is a base layer rather than the whole result.
uses: The paper appears to rely on the theorem as machinery.
contradicts: The paper's claim conflicts with a theorem or certificate in the canon.
unclear: Pith found a possible connection, but the passage is too broad, indirect, or ambiguous to say the theorem truly supports the claim.

Reference graph

Works this paper leans on

24 extracted references · 24 canonical work pages · 2 internal anchors

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CRC Press, New York (2008 )

Alpert, C.J., Mehta, D.P., Sapatnekar, S.S.: Handbook of Algo- rithms for Physical Design Automation. CRC Press, New York (2008 ). https://doi.org/10.1201/9781420013481 19

work page doi:10.1201/9781420013481 2008
[2]

Springer, Heidelberg, Germany (2011)

Kahng, A.B., Lienig, J., Markov, I.L., Hu, J.: VLSI Physical Design: F rom Graph Partitioning to Timing Closure. Springer, Heidelberg, Germany (2011). https://doi.org/10.1007/978-90-481-9591-6

work page doi:10.1007/978-90-481-9591-6 2011
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I n: 2007 Asia and South Paciﬁc Design Automation Conference, pp

Viswanathan, N., Pan, M., Chu, C.: FastPlace 3.0: A fast multilevel quadratic placement algorithm with placement congestion control. I n: 2007 Asia and South Paciﬁc Design Automation Conference, pp. 135–140 (2007). https://doi.org/10.1109/ASPDAC.2007.357975 . IEEE

work page doi:10.1109/aspdac.2007.357975 2007
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Caldwell, A.E., Kahng, A.B., Markov, I.L.: Optimal partitioners and en d-case placers for standard-cell layout. In: Proceedings of the 1999 In ternational Sympo- sium on Physical Design, pp. 90–96 (1999). https://doi.org/10.1109/43.892854

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Operations Research Tran sactions 25(03), 15–36 (2021) https://doi.org/10.15960/j.cnki.issn.1007-6093.2021.03.002

Huang, Z., Li, X., Zhu, W.: Optimization models and algorithms for plac ement of very large scale integrated circuits. Operations Research Tran sactions 25(03), 15–36 (2021) https://doi.org/10.15960/j.cnki.issn.1007-6093.2021.03.002

work page doi:10.15960/j.cnki.issn.1007-6093.2021.03.002 2021
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In: Proceedings of the 2005 International Sympo sium on Physical Design, pp

Chan, T., Cong, J., Sze, K.: Multilevel generalized force-directed method for cir- cuit placement. In: Proceedings of the 2005 International Sympo sium on Physical Design, pp. 185–192 (2005). https://doi.org/10.1109/IPDPS.2013.70

work page doi:10.1109/ipdps.2013.70 2005
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Google Patents

Naylor, W.C., Donelly, R., Sha, L.: Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer. Google Patents. US Patent 6,301,693 (2001). https://doi.org/US6301693

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Hsu, M.-K., Chang, Y.-W., Balabanov, V.: TSV-aware analytical pla cement for 3d IC designs. In: Proceedings of the 48th Design Automation Conf erence, pp. 664–669 (2011)

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Chen, T.-C., Jiang, Z.-W., Hsu, T.-C., Chen, H.-C., Chang, Y.-W.: NTU place3: An analytical placer for large-scale mixed-size designs with preplace d blocks and density constraints. IEEE Trans. Comput. Aided Des. Integr. Cir cuits Syst. 27(7), 1228–1240 (2008) https://doi.org/10.1109/TCAD.2008.923063

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Zhu, W., Chen, J., Peng, Z., Fan, G.: Nonsmooth optimization meth od for VLSI global placement. IEEE Trans. Comput.-Aided Des. Integr. Circuit s Syst. 34(4), 642–655 (2015) https://doi.org/10.1109/TCAD.2015.2394484

work page doi:10.1109/tcad.2015.2394484 2015
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Sun, J., Cheng, H., Wu, J., Zhu, Z., Chen, Y.: Floorplanning of VLSI by mixed- variable optimization. In: International Symposium on Intelligence C omputation 20 and Applications, pp. 137–151 (2023). Springer

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Chang, Y.-W., Jiang, Z.-W., Chen, T.-C.: Essential issues in analytic al place- ment algorithms. IPSJ Trans. Syst. LSI Des. Methodol. 2, 145–166 (2009) https://doi.org/10.2197/ipsjtsldm.2.145

work page doi:10.2197/ipsjtsldm.2.145 2009
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In: Pro- ceedings of the 56th Annual Design Automation Conference 2019, pp

Lin, Y., Dhar, S., Li, W., Ren, H., Khailany, B., Pan, D.Z.: Dreamplace: Deep learning toolkit-enabled GPU acceleration for modern VLSI placemen t. In: Pro- ceedings of the 56th Annual Design Automation Conference 2019, pp. 1–6 (2019). https://doi.org/10.1109/TCAD.2020.3003843

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work page doi:10.1137/20m1383069 2022
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In: Pro- ceedings of the 51st Annual Design Automation Conference, pp

Lu, J., Chen, P., Chang, C.-C., Sha, L., Huang, D.J.-H., Teng, C.-C., Cheng, C.-K.: ePlace: Electrostatics based placement using Nesterov’s met hod. In: Pro- ceedings of the 51st Annual Design Automation Conference, pp. 1 –6 (2014). https://doi.org/10.1145/2593069.2593216

work page doi:10.1145/2593069.2593216 2014
[21]

Zhou, T., Ren, J., Medo, M., Zhang, Y.-C.: Bipartite network proj ection and personal recommendation. Phys. Rev. E Stat. Nonlin. Soft Matte r Phys. 76(4), 046115 (2007) https://doi.org/10.1103/PhysRevE.76.046115

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[23]

Xiao, S., Wang, H., Wang, W., Huang, Z., Zhou, X., Xu, M.: Arti- ﬁcial bee colony algorithm based on adaptive neighborhood search and gaussian perturbation. Appl. Soft Comput. 100, 106955 (2021) https://doi.org/10.1016/j.asoc.2020.106955

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[25]

Adam: A Method for Stochastic Optimization

Kingma, D.P., Ba, J.: Adam: a method for stochastic optimization. arXiv:1412.6980 [cs] (2014). Accessed 2018-04-24 21 0 100 200 300 400 500 600 700 800 W idth 0 100 200 300 400 500 600 700 800 Height RBSM: hpwl = 323264.41 overlap = 1058.74 /c55/c1c/c56 /c4d/c52/c79/c79 /c60/c32/c62/c6d/c48/c69 0 100 200 300 400 500 600 700 800 W idth 0 100 200 300 400 50...

work page internal anchor Pith review Pith/arXiv arXiv 2014

[1] [1]

CRC Press, New York (2008 )

Alpert, C.J., Mehta, D.P., Sapatnekar, S.S.: Handbook of Algo- rithms for Physical Design Automation. CRC Press, New York (2008 ). https://doi.org/10.1201/9781420013481 19

work page doi:10.1201/9781420013481 2008

[2] [2]

Springer, Heidelberg, Germany (2011)

Kahng, A.B., Lienig, J., Markov, I.L., Hu, J.: VLSI Physical Design: F rom Graph Partitioning to Timing Closure. Springer, Heidelberg, Germany (2011). https://doi.org/10.1007/978-90-481-9591-6

work page doi:10.1007/978-90-481-9591-6 2011

[3] [3]

Sechen, C.: VLSI Placement and Global Routing Using Simulated Ann ealing vol

work page

[4] [4]

Springer, New York, NY (2012)

work page 2012

[5] [6]

I n: 2007 Asia and South Paciﬁc Design Automation Conference, pp

Viswanathan, N., Pan, M., Chu, C.: FastPlace 3.0: A fast multilevel quadratic placement algorithm with placement congestion control. I n: 2007 Asia and South Paciﬁc Design Automation Conference, pp. 135–140 (2007). https://doi.org/10.1109/ASPDAC.2007.357975 . IEEE

work page doi:10.1109/aspdac.2007.357975 2007

[6] [7]

In: Proceedings of the 1999 In ternational Sympo- sium on Physical Design, pp

Caldwell, A.E., Kahng, A.B., Markov, I.L.: Optimal partitioners and en d-case placers for standard-cell layout. In: Proceedings of the 1999 In ternational Sympo- sium on Physical Design, pp. 90–96 (1999). https://doi.org/10.1109/43.892854

work page doi:10.1109/43.892854 1999

[7] [8]

Operations Research Tran sactions 25(03), 15–36 (2021) https://doi.org/10.15960/j.cnki.issn.1007-6093.2021.03.002

Huang, Z., Li, X., Zhu, W.: Optimization models and algorithms for plac ement of very large scale integrated circuits. Operations Research Tran sactions 25(03), 15–36 (2021) https://doi.org/10.15960/j.cnki.issn.1007-6093.2021.03.002

work page doi:10.15960/j.cnki.issn.1007-6093.2021.03.002 2021

[8] [9]

In: Proceedings of the 2005 International Sympo sium on Physical Design, pp

Chan, T., Cong, J., Sze, K.: Multilevel generalized force-directed method for cir- cuit placement. In: Proceedings of the 2005 International Sympo sium on Physical Design, pp. 185–192 (2005). https://doi.org/10.1109/IPDPS.2013.70

work page doi:10.1109/ipdps.2013.70 2005

[9] [10]

Google Patents

Naylor, W.C., Donelly, R., Sha, L.: Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer. Google Patents. US Patent 6,301,693 (2001). https://doi.org/US6301693

work page 2001

[10] [11]

In: Proceedings of the 48th Design Automation Conf erence, pp

Hsu, M.-K., Chang, Y.-W., Balabanov, V.: TSV-aware analytical pla cement for 3d IC designs. In: Proceedings of the 48th Design Automation Conf erence, pp. 664–669 (2011)

work page 2011

[11] [12]

IEEE Trans

Chen, T.-C., Jiang, Z.-W., Hsu, T.-C., Chen, H.-C., Chang, Y.-W.: NTU place3: An analytical placer for large-scale mixed-size designs with preplace d blocks and density constraints. IEEE Trans. Comput. Aided Des. Integr. Cir cuits Syst. 27(7), 1228–1240 (2008) https://doi.org/10.1109/TCAD.2008.923063

work page doi:10.1109/tcad.2008.923063 2008

[12] [13]

IEEE Trans

Zhu, W., Chen, J., Peng, Z., Fan, G.: Nonsmooth optimization meth od for VLSI global placement. IEEE Trans. Comput.-Aided Des. Integr. Circuit s Syst. 34(4), 642–655 (2015) https://doi.org/10.1109/TCAD.2015.2394484

work page doi:10.1109/tcad.2015.2394484 2015

[13] [14]

In: International Symposium on Intelligence C omputation 20 and Applications, pp

Sun, J., Cheng, H., Wu, J., Zhu, Z., Chen, Y.: Floorplanning of VLSI by mixed- variable optimization. In: International Symposium on Intelligence C omputation 20 and Applications, pp. 137–151 (2023). Springer

work page 2023

[14] [15]

Paszke, A., Gross, S., Massa, F., Lerer, A., Bradbury, J., Chan an, G., Killeen, T., Lin, Z., Gimelshein, N., Antiga, L., et al.: Pytorch: An imperative style , high- performance deep learning library. Adv. Neural Inf. Process. Sy st. 32 (2019) https://doi.org/10.48550/arXiv.1912.01703

work page internal anchor Pith review Pith/arXiv arXiv doi:10.48550/arxiv.1912.01703 2019

[15] [16]

Salama, H.F., Reeves, D.S., Viniotis, Y.: GSRC ﬂoorplan benchmarks (1997)

work page 1997

[16] [17]

IPSJ Trans

Chang, Y.-W., Jiang, Z.-W., Chen, T.-C.: Essential issues in analytic al place- ment algorithms. IPSJ Trans. Syst. LSI Des. Methodol. 2, 145–166 (2009) https://doi.org/10.2197/ipsjtsldm.2.145

work page doi:10.2197/ipsjtsldm.2.145 2009

[17] [18]

In: Pro- ceedings of the 56th Annual Design Automation Conference 2019, pp

Lin, Y., Dhar, S., Li, W., Ren, H., Khailany, B., Pan, D.Z.: Dreamplace: Deep learning toolkit-enabled GPU acceleration for modern VLSI placemen t. In: Pro- ceedings of the 56th Annual Design Automation Conference 2019, pp. 1–6 (2019). https://doi.org/10.1109/TCAD.2020.3003843

work page doi:10.1109/tcad.2020.3003843 2019

[18] [19]

Multiscale Model

Jin, S., Li, L., Sun, Y.: On the random batch method for second or der interacting particle systems. Multiscale Model. Simul. 20(2), 741–768 (2022) https://doi.org/10.1137/20M1383069

work page doi:10.1137/20m1383069 2022

[19] [20]

In: Pro- ceedings of the 51st Annual Design Automation Conference, pp

Lu, J., Chen, P., Chang, C.-C., Sha, L., Huang, D.J.-H., Teng, C.-C., Cheng, C.-K.: ePlace: Electrostatics based placement using Nesterov’s met hod. In: Pro- ceedings of the 51st Annual Design Automation Conference, pp. 1 –6 (2014). https://doi.org/10.1145/2593069.2593216

work page doi:10.1145/2593069.2593216 2014

[20] [21]

Zhou, T., Ren, J., Medo, M., Zhang, Y.-C.: Bipartite network proj ection and personal recommendation. Phys. Rev. E Stat. Nonlin. Soft Matte r Phys. 76(4), 046115 (2007) https://doi.org/10.1103/PhysRevE.76.046115

work page doi:10.1103/physreve.76.046115 2007

[21] [22]

Weiss, P.: L’hypoth` ese du champ mol´ eculaire et la propri´ et´ e ferromagn´ etique. J. Phys. Theor. Appl. 6(1), 661–690 (1907) https://doi.org/10.1051/jphystap:019070060066100

work page doi:10.1051/jphystap:019070060066100 1907

[22] [23]

Xiao, S., Wang, H., Wang, W., Huang, Z., Zhou, X., Xu, M.: Arti- ﬁcial bee colony algorithm based on adaptive neighborhood search and gaussian perturbation. Appl. Soft Comput. 100, 106955 (2021) https://doi.org/10.1016/j.asoc.2020.106955

work page doi:10.1016/j.asoc.2020.106955 2021

[23] [24]

Numerical Optimization

Nocedal, J., Wright, S.J.: Numerical Optimization. Springer, New Y ork, NY (1999). https://doi.org/10.1007/978-0-387-40065-5

work page doi:10.1007/978-0-387-40065-5 1999

[24] [25]

Adam: A Method for Stochastic Optimization

Kingma, D.P., Ba, J.: Adam: a method for stochastic optimization. arXiv:1412.6980 [cs] (2014). Accessed 2018-04-24 21 0 100 200 300 400 500 600 700 800 W idth 0 100 200 300 400 500 600 700 800 Height RBSM: hpwl = 323264.41 overlap = 1058.74 /c55/c1c/c56 /c4d/c52/c79/c79 /c60/c32/c62/c6d/c48/c69 0 100 200 300 400 500 600 700 800 W idth 0 100 200 300 400 50...

work page internal anchor Pith review Pith/arXiv arXiv 2014