Analog Alchemy: Neural Computation with In-Memory Inference, Learning and Routing

Yigit Demirag

REVIEW 4 major objections 5 minor 297 references

Analog Alchemy: Neural Computation with In-Memory Inference, Learning and Routing

T0 review · 4 major / 5 minor · reviewed 2026-08-10 · deepseek-v4-flash

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Pith's one-line read A thesis makes the case that memristive devices can do neural inference, online learning, and spike routing inside the memory itself, and backs it with measurements from fabricated arrays.

desk verdict A credible PhD compilation: real device measurements and a promising architecture, but the headline routing-energy advantage is extrapolated from tile-level data and full methods are deferred to earlier papers. read the letter →

arxiv 2412.20848 v1 pith:XK6M6OMD submitted 2024-12-30 cs.NE cs.AIcs.ET

Yigit Demirag This is my paper · ORCID

classification cs.NEcs.AIcs.ET

keywords memristivedevicesin-memorycomputingspikingneuralnetworksonlinelearningphase-changememoryRRAMreservoirsmall-worldrouting

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper argues that the physical dynamics of memristive devices can be used for the full set of operations a neural computer needs, not just for storing weights: inference, learning, and communication. It claims that with the right programming techniques, circuits, and training algorithms, the non-idealities of analog devices become manageable, and it provides hardware evidence from RRAM, PCM, and perovskite devices. If true, this would replace energy-hungry data movement between memory and processor with computation in place, opening a path to much more efficient edge AI and to scalable spiking neural networks. The thesis also claims that a memristive routing fabric called Mosaic can move spikes between compute tiles with at least an order of magnitude less energy than other spiking hardware platforms.

What carries the argument

The unifying machinery is the use of a memristor's conductance as a physical state variable that does different jobs depending on how it is driven. Compliance-current ($I_\text{CC}$) programming sets the size of the conductive filament, turning binary RRAM and perovskite devices into multi-level weights. A statistical PCM model captures programming noise, read noise, and drift, and mixed-precision gradient accumulation bridges the gap between the precision of the e-prop learning rule, a spatio-temporally local gradient estimate for recurrent spiking networks, and the device's coarse programmable steps. PCM's structural-relaxation drift, described by $R(t)=R(t_0)(t/t_0)^\nu$, is repurposed from a bug into an eligibility-trace memory. Finally, the Mosaic architecture replaces one large crossbar with a mesh of small Neuron Tiles and Routing Tiles, where RRAM states both compute synaptic currents and decide whether a spike is passed or blocked, implementing small-world connectivity directly in the wiring.

What would settle it

Fabricate a Mosaic with the full intended number of Neuron and Routing Tiles, measure the energy per routed spike at the system level, and compare it to the simulated one-to-four-orders-of-magnitude gain over other platforms; a smaller measured gain would falsify the routing-efficiency claim. For the learning claims, train an RSNN with e-prop and mixed-precision updates on a large PCM array and check whether the test error stays within the range predicted by the simulation framework.

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Extended reading notes

Core claim

The central claim is that a memristive substrate can be more than a weight store: its physics can carry out the three operations a neural computer needs, and the non-idealities that analog operation introduces can be absorbed by co-designing devices, circuits, and learning rules. Concretely, the thesis reports that compliance-current programming converts intrinsically binary HfO2 RRAM and halide-perovskite devices into multi-level conductances; that the e-prop local learning rule trains recurrent spiking networks on realistic PCM crossbars when gradients are accumulated in high-precision memory and only applied when they exceed the device's minimum programmable conductance change; that PCM's natural conductance drift can serve as a scalable eligibility trace; that a single CsPbBr3 nanocrystal material can be switched between volatile and non-volatile modes; and that the Mosaic systolic mesh, trained with layout-aware methods, implements small-world connectivity so that routing spikes between crossbars costs at least an order of magnitude less energy than on other spiking hardware platforms.

Load-bearing premise

The load-bearing premise is that the statistical device models and small-array measurements used throughout the thesis faithfully represent how the devices would behave in a full-scale system; if device-to-device variation, drift, or yield are worse at scale than the models assume, the reported accuracies and routing-energy gains are optimistic.

Editorial extensions

If this is right

If the thesis's claims hold, online gradient-based training of recurrent spiking networks becomes feasible on memristive crossbars, and mixed-precision gradient accumulation cuts the number of device write pulses by two to three orders of magnitude.
Compliance-current programming gives a common recipe for raising the effective bit precision of binary RRAM and perovskite devices, removing a major obstacle to on-chip learning.
PCM drift can implement multi-second eligibility traces at more than 10 times the area efficiency of capacitor-based CMOS traces, making three-factor learning rules easier to scale.
A single halide-perovskite material can serve both as a volatile reservoir element and as a non-volatile readout weight, so heterogeneous neural dynamics can be built in one fabrication process.
Spike routing between crossbars can be done in memory with at least an order of magnitude less energy than other spiking platforms, at competitive accuracy on ECG anomaly detection, keyword spotting, and a motor-control reinforcement-learning task.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

An implication the author leaves implicit is that the small-world connectivity prior could become a default layout principle for neuromorphic chips, with sparsity enforced by the physical mesh rather than discovered by pruning after training.
A testable extension is to run a reinforcement-learning task with delayed reward on hardware that combines PCM-trace eligibility traces with a third-factor signal, since the multi-second trace timescales are exactly what distal-reward tasks require.
The perovskite reconfigurability suggests a runtime-reconfigurable substrate where the same die can switch between volatile short-term computation and non-volatile storage, which would be worth testing by cycling devices between modes many times and checking drift and endurance.
If the mixed-precision result transfers broadly, a small high-precision gradient buffer may become a standard companion to analog in-memory training, accepting a digital component in exchange for far fewer analog programming events.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Quick take: this is a dissertation made of six already-published papers, not a new result, but it is a fair and useful synthesis. The hardware evidence is genuine: 4kb HfO2 RRAM arrays with compliance-current programming, e-prop training on the IBM HERMES chip, PCM drift traces, perovskite endurance up to 2M cycles, and fabricated Mosaic neuron/routing tiles in 130nm CMOS. The unified framing around gradient-based learning and connectomics actually helps; it makes the trade-offs between device physics, circuits, and learning rules easier to see.

The soft spots are concentrated in the system-level claims. The Mosaic ≥10x routing-energy advantage is not an end-to-end measurement; it comes from simulations calibrated against single fabricated tiles and a 4096-device array. The stress-test note is right that this needs array-level effects (IR drop, yield, inter-tile wire energy, comparator overhead) and equivalent accounting when comparing to other SNN platforms. That doesn't make the claim wrong—the tile measurements are real and the architecture is sensible—but the strength of the inference is weaker than the abstract suggests. Also, Chapters 4 and 5 explicitly defer full experimental methods to earlier Nature Communications papers, and several comparison tables report best-selected hyperparameters without error bars. These are real limitations for a standalone arXiv document, but they are mostly presentation and auditability issues, not evidence of a broken argument.

I'd trust the device work. The statistical models come from published measurements, and the dependency on fitted parameters is not circular. Self-citation is fine here because the cited results are peer-reviewed and, in the HERMES and perovskite cases, externally validated.

Who should read this: someone entering neuromorphic hardware who wants one place to see how device programming, local learning rules, and interconnect design fit together. A specialist should go to the original papers for methods. If this landed as a journal submission, I'd send it to referees rather than desk reject, but the editor should expect revisions that put the system-level simulation assumptions on the table and add the missing methods and error bars.

Referee Report

4 major / 5 minor

Summary. This manuscript is a cumulative PhD thesis presenting four lines of work on memristive hardware for neural computation. Chapter 2 proposes programming binary HfO2 RRAMs by compliance current to obtain multi-level conductance for delta-rule on-chip learning, validated by 4kb array measurements and MNIST simulations. Chapter 3 develops a PyTorch PCM crossbar simulation framework to compare weight-update schemes for e-prop learning, validates mixed-precision training on the HERMES PCM chip, and introduces PCM-trace, a drift-based eligibility trace building block. Chapter 4 reports a halide-perovskite memristor that reconfigures between volatile and non-volatile modes, with record endurance claims and a reservoir-computing classification demo. Chapter 5 introduces Mosaic, a systolic mesh of RRAM neuron and routing tiles, with fabricated tile measurements, hardware-aware simulations on edge benchmarks, and a claimed at-least-one-order-of-magnitude routing-energy improvement over other SNN platforms.

Significance. If the results hold, the thesis provides valuable experimental evidence that memristive non-idealities can be turned into features rather than obstacles. The concrete strengths are the fabricated hardware measurements (4kb HfO2 array ICC curves, HERMES e-prop experiments, PCM drift traces, perovskite endurance, and Mosaic neuron/routing tiles), the statistical device models calibrated to measurements, the open-source PCM simulation framework, and the explicit comparison of weight-update schemes. The strongest specific claim, the Mosaic routing-energy advantage, would be an important scaling result for neuromorphic systems. However, the standalone arXiv version omits full methods for Chapters 4 and 5 and does not provide error bars for several key simulation numbers, so the auditability of the system-level extrapolation is limited.

major comments (4)

[§5.1 and §5.4] The abstract and §5.1 claim that Mosaic achieves at least one order of magnitude higher routing energy efficiency than other SNN platforms, and §5.4 benchmarks this via system-level simulations calibrated on single fabricated tiles and a 4096-device RRAM array. The thesis omits the full energy model and the comparison protocol, since the Methods section (§5.6) is not included in this version. The reader therefore cannot verify whether the comparison accounts for neuron and synapse circuits, comparators, read/write energy, control and clocking, static power, inter-tile wire energy, and equivalent spike traffic and technology nodes across platforms. Please provide the complete energy accounting and the comparison criteria, or explicitly scope the claim as a projected system-level estimate rather than a directly measured end-to-end result.
[§4.7 and chapter header for Chapter 4] The chapter header states that the original publication contains the full experimental details, which are omitted 'for clarity,' and §4.7 reports a single reservoir-computing test accuracy of 85.1% based on 25 devices and 19,900 measurements. Because this accuracy is a central demonstration of the perovskite device's utility, the omitted details are load-bearing: the thesis should report the number of devices per condition, the device yield, the variability of accuracy across devices and cycles, and the exact train/test split. Without these, the claim that the Icc-modulated readout training is effective cannot be independently assessed from this manuscript.
[§3.1.3.4 and Tables 3.1–3.2] Tables 3.1 and 3.2 report single MSE values for each weight-update method, but the text says that the loss is averaged over the ten best network hyperparameters and that 1000 networks were trained per method. The absence of error bars or confidence intervals makes the key comparison (mixed-precision being the only method below the MSE<0.1 threshold under PCM non-idealities) unverifiable, especially since Fig. 3.4 shows substantial run-to-run variation. Please report the mean, standard deviation, and number of runs for each table entry.
[§2.5] The MNIST result of 92.68% is reported as a single number, for only the first five classes, with no FP32 backpropagation baseline in the same figure or table, despite the stated goal of matching FP32 accuracy. The Gaussian cycle-to-cycle variability model is fitted to a single 4kb array, and its generalization to larger arrays is assumed without discussion. Please report the mean and standard deviation over multiple training seeds, and include the FP32 reference accuracy on the same five-class subset to support the claim of comparability.

minor comments (5)

[Chapters 2–4, throughout] There are numerous typographical errors, including 'programning,' 'dialectric,' and 'challanges'; the manuscript should be carefully proofread.
[§2.3, Algorithm 1] The pseudocode initializes weights with 'rand()' but does not specify the distribution or range; the scaling constants c1 and c2 are also not tied to the measured ICC-to-conductance range, which should be clarified.
[§3.3.2, Eq. (3.7)] The symbol tp is used in the conductance difference equation but is not defined in the text; please define it as the time of the last programming event and state the units of Delta t.
[§3.2, Figure 3.10d] The panel showing the number of SET pulses lacks axis labels and units; please specify that the quantity is pulses per training iteration.
[§5.2, Figure 5.3d] Please state explicitly how the comparator reference current Ire f is derived from the HCS/LCS CDFs and how sensitive the pass/block decision is to device drift and temperature; a one-sentence robustness statement would suffice.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: measured device models are used as forward simulation substrates, and reported accuracies are evaluations, not fitted predictions.

full rationale

The thesis's derivation chain is not circular. Device statistics (the 4kb HfO2 ReRAM Icc-to-GLRS mapping in Chapter 2, the Nandakumar PCM model in Chapter 3, and the 25-device perovskite statistics in Chapter 4) are measured and then used as forward simulation substrates; the resulting MNIST, pattern-generation, and firing-pattern accuracies are evaluations of trained systems under those measured statistics, not predictions of the same fitted quantities. The Mosaic routing-efficiency comparison is an extrapolation from fabricated tile measurements through a system-level energy model; the extrapolation rests on scalability assumptions (array-level effects, overhead accounting) rather than on a circular reduction. Self-citations identify the prior publications from which chapters are drawn, but the load-bearing device data and algorithm implementations are presented in the thesis itself; no uniqueness theorem or ansatz is imported solely through self-citation. The thesis also flags omitted experimental detail (the Chapter 4 preamble states that experimental details are omitted for clarity), which limits independent auditability but does not make any step equivalent to its input by construction.

Assumptions & free parameters 5 free parameters · 5 assumptions · 3 invented entities

The central claims rely almost entirely on empirically fitted device models and calibrated simulations. No equation in the thesis derives the reported performance from first principles; the numbers enter through measured conductance distributions, PCM drift exponents, and chosen learning hyperparameters. The main invented entities are hardware building blocks, each backed by direct measurements, but their system-level advantages are extrapolated through simulation.

free parameters (5)

ICC to HCS conductance power-law mapping (ReRAM) = power-law fit over ICC range 10-400 uA (exponent and scale not quoted)
Controls the effective multi-bit weight precision claim in Chapter 2; fit to 4kb HfO2 ReRAM array measurements (Fig. 2.1) and used in MNIST simulations.
PCM SET conductance increment = 0.75 uS per pulse (assumed linear)
Used in mixed-precision and multi-memristor update methods in Section 3.1.3.2; from the PCM model in Nandakumar et al. [81], not independently measured in this thesis.
PCM drift coefficient nu = not quoted; fit to 3 device measurements
Defines the decay timescale of PCM-trace eligibility traces in Section 3.3; empirical drift model R(t)=R(t0)(t/t0)^nu.
Perovskite Icc-to-conductance linear mapping = linear coefficients from 25 devices
Used to train readout in Chapter 4 by mapping desired conductance to programming compliance current.
Learning rate and error threshold delta_th = tuned per chapter, values not tabulated
Learning rate eta and stop-learning threshold delta_th are hand-set hyperparameters in Chapters 2 and 3; central to reported accuracies.

assumptions (5)

domain assumption Statistical device models trained on small arrays (4kb ReRAM, PCM from [81], 25 perovskite devices) accurately represent the population behavior of large arrays.
Chapter 2 uses fitted Gaussian distributions from a 4kb array; Chapter 3 uses Nandakumar et al.'s 10,000-device PCM model; Chapter 4 uses 25 devices. The system-level accuracy and energy conclusions depend on this extrapolation.
standard math The e-prop local learning rule provides a sufficient gradient approximation for online RSNN training on analog substrates.
Adopted from Bellec et al. [75] and used throughout Chapter 3; if the surrogate gradients are too biased, the hardware learning results would not transfer.
domain assumption Small-world connectivity retains task performance while reducing memory and routing energy.
Mosaic (Chapter 5) is built on this prior; the training results show only small accuracy drops, but the assumption bounds how much sparsity can be enforced.
domain assumption The virtual node reservoir with a single volatile memristor captures temporal features of input spike trains.
Chapter 4 uses Appeltant et al. [239]'s delay-line reservoir concept; classification accuracy depends on the fading memory and nonlinearity being sufficient.
domain assumption Energy comparisons across SNN platforms use comparable routing workloads and include the same overheads.
Chapter 5 claims at least 10x routing energy improvement over other platforms; the truncated text does not show the full benchmarking details.

invented entities (3)

OGB-capped CsPbBr3 perovskite reconfigurable memristor independent evidence
purpose: Single material that can be switched between volatile diffusive (reservoir) and non-volatile drift (readout) modes with record endurance.
The thesis reports direct electrical measurements: 2x10^6 volatile cycles, 5.6x10^3 non-volatile cycles, switching at low voltages, plus SIMS and temperature data. Mechanism is not fully understood (admitted in Section 4.8).
PCM-trace eligibility trace block independent evidence
purpose: Implements slow synaptic eligibility traces on a small footprint by exploiting PCM conductance drift instead of large capacitors.
Supported by drift measurements on three CEA-LETI PCM devices and circuit simulations; requires additional characterization for production.
Mosaic small-world systolic architecture independent evidence
purpose: Network of distributed neuron and routing crossbar tiles for energy-efficient spike routing with locally dense, globally sparse connectivity.
Fabricated neuromorphic tiles in 130nm CMOS with integrated RRAM; system-level performance from calibrated simulations, not a full Mosaic chip.

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Cite this review

Pith. "Pith review of Analog Alchemy: Neural Computation with In-Memory Inference, Learning and Routing." pith.science (2026). https://pith.science/paper/XK6M6OMD

@misc{pith2026241220848,
  author       = {Pith},
  title        = {Pith review of: Analog Alchemy: Neural Computation with In-Memory Inference, Learning and Routing},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/XK6M6OMD}},
  note         = {Machine review of arXiv:2412.20848}
}

read the original abstract

As neural computation is revolutionizing the field of Artificial Intelligence (AI), rethinking the ideal neural hardware is becoming the next frontier. Fast and reliable von Neumann architecture has been the hosting platform for neural computation. Although capable, its separation of memory and computation creates the bottleneck for the energy efficiency of neural computation, contrasting the biological brain. The question remains: how can we efficiently combine memory and computation, while exploiting the physics of the substrate, to build intelligent systems? In this thesis, I explore an alternative way with memristive devices for neural computation, where the unique physical dynamics of the devices are used for inference, learning and routing. Guided by the principles of gradient-based learning, we selected functions that need to be materialized, and analyzed connectomics principles for efficient wiring. Despite non-idealities and noise inherent in analog physics, I will provide hardware evidence of adaptability of local learning to memristive substrates, new material stacks and circuit blocks that aid in solving the credit assignment problem and efficient routing between analog crossbars for scalable architectures.

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