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REVIEW 4 major objections 6 minor 41 references

12-bit Delta-Sigma ADC operating at a temperature of up to 250C in Standard 0.18 $\mu$m SOI CMOS

T0 review · 4 major / 6 minor · reviewed 2026-08-10 · deepseek-v4-flash

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Pith's one-line read A 12-bit delta-sigma ADC delivers full accuracy at 250 °C.

desk verdict A credible 12-bit delta-sigma ADC demo at 250°C in a 175°C-qualified 0.18µm SOI process, but the reliability claim needs soak data and the power unit typo needs fixing. read the letter →

arxiv 2501.00482 v1 pith:IPGBJVMA submitted 2024-12-31 eess.SP cs.AR

Christian Sbrana , Alessandro Catania , Tommaso Toschi , Sebastiano Strangio , Giuseppe Iannaccone This is my paper · ORCID
classification eess.SPcs.AR
keywords high-temperatureelectronicsdelta-sigmaADCSOICMOSleakagecompensationclockboostingelectromigrationharsh-environmentsensingSchreierfigureofmerit
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper claims that a second-order discrete-time delta-sigma ADC fabricated in a 0.18 µm SOI CMOS process qualified only to 175 °C can deliver 12-bit accuracy at 250 °C. In measurements on five samples, SNR stays above 93 dB and SINAD is 74.5 dB at 250 °C, with an effective number of bits of 12. The converter draws 44 µW according to Table I and occupies 0.065 mm², with only 13.7% of the die area devoted to high-temperature hardening. If the claim holds, harsh-environment systems in oil and gas extraction, aeronautics, and industrial ovens could use inexpensive automotive-grade CMOS instead of specialized wide-bandgap or bulky high-temperature SOI parts, at the cost of a lower conversion bandwidth.

What carries the argument

The central object is a second-order, single-bit, cascade-of-integrators feedback delta-sigma modulator implemented as a fully differential switched-capacitor circuit with a StrongARM latch comparator and an on-chip digital low-pass filter. The argument is carried by three temperature-hardening mechanisms: dummy-transistor leakage compensation, which injects equal-and-opposite junction currents into source/drain-body junctions and uses a current mirror with ratio four to cancel leakage at the differential input pair; clock boosting, which shifts the pass-gate clock high level to $V_{DD}+V_{ref}$ and the low level to $-V_{ref}$, cutting subthreshold channel leakage by more than a factor of twenty at a 200 mV boost; and metal-line sizing that keeps current density a factor of ten below an electromigration threshold extrapolated to 300 °C. These mechanisms protect the switched-capacitor charge, which is what the delta-sigma conversion accuracy ultimately depends on.

What would settle it

Power five packaged samples at 250 °C in an oven with clocks and inputs running, then measure SNR, SINAD, INL, and supply current every few hours for 1000 hours and thermal-cycle between −40 °C and 250 °C; if ENOB drops below 12 bits, INL exceeds 1 mV, or an interconnect resistance shift or open appears during the soak, the claim of reliable operation up to 250 °C is falsified.

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Extended reading notes

Core claim

On the paper's own terms, the discovery is that a standard automotive SOI CMOS process can be pushed 75 °C above its qualification limit without losing data-converter performance, provided the design counters junction leakage, subthreshold leakage, and electromigration. Across five packaged samples characterized from −40 °C to 260 °C, SNR exceeds 93 dB up to 250 °C while SINAD degrades softly from about 85 dB at room temperature to 74.5 dB at 250 °C; the worst-case INL stays below 1 mV and supply current remains nearly flat. Above 250 °C the performance collapses, which the authors attribute to leakage through pad-protection diodes and unintended turn-on of nominally off blocks. Because the PDK is calibrated only to 175 °C, these measurements, not simulations, are what support the 12-bit ENOB at 250 °C.

Load-bearing premise

The load-bearing premise is that the converter's measured 250 °C performance persists over application-relevant lifetimes, which the paper supports only with short temperature-step measurements and extrapolated electromigration rules, not with soak or thermal-cycling data.

Editorial extensions

If this is right

  • A 12-bit delta-sigma ADC can be embedded in a high-temperature sensor node built on a standard automotive CMOS process, removing the need for SiC or GaN conversion electronics in many oil-and-gas and aeronautics signal chains.
  • The hardening techniques transfer to other switched-capacitor and mixed-signal blocks, so op-amps, references, and SAR front-ends on the same process can adopt the same leakage compensation and clock boosting.
  • With 44 µW and 0.065 mm², the converter is small and efficient enough for battery- or energy-harvesting-powered loggers that sit inside ovens or wells.
  • Because the area cost of the high-temperature circuitry is only 13.7%, temperature hardening does not force a larger, more expensive die.
  • Raising the CMFB clock frequency above the signal band should remove the pair of distortion spurs seen in the spectra, giving headroom for further SINAD improvement.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The abstract states a power of 44 mW, while Table I reports 0.044 mW; the 140 dB Schreier FoM only closes if the power is 44 µW, so the milliwatt figure is almost certainly a typographical error that should be corrected before the power claim is relied upon.
  • Functional measurements at temperature steps demonstrate performance at 250 °C but not lifetime at 250 °C; 'reliable operation' is a projection from extrapolated electromigration rules until soak, thermal-cycling, or long-duration data are reported.
  • A natural next experiment is a 1000-hour powered soak at 250 °C with periodic SNR, SINAD, INL, and supply-current checks; if those hold, the same hardening recipe could plausibly be extended toward 300 °C, as the authors suggest, possibly with more temperature-resistant interconnect.
  • The leakage-compensation current mirror at the input pair injects nonideal mirrored currents that could become a nonlinearity source at resolutions beyond 12 bits, so calibration or chopping may be needed for higher-performance variants.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 6 minor

Summary. The paper presents a second-order discrete-time delta-sigma ADC fabricated in XFAB XT018 0.18 µm SOI CMOS, with the stated goal of operating at temperatures up to 250 °C, well above the 175 °C qualification limit of the process. The authors describe design techniques for high-temperature operation, including dummy-transistor junction-leakage compensation, clock-boosting for pass-gate subthreshold leakage, and electromigration-aware metal sizing. Measurements on five samples report SNR above 93 dB, SINAD of 74.5 dB (ENOB of 12 bits), a Schreier FoM of 140 dB at 250 °C, a die area of 0.065 mm², and a power consumption that appears in the abstract and conclusions as 44 mW but in Table I as 0.044 mW. The paper claims a record-low area and power for a high-temperature data converter and positions the design for applications such as oil/gas extraction and aeronautics.

Significance. If the measured performance is reproducible, this is a valuable engineering contribution: a 12-bit ADC operating at 250 °C in a standard automotive-grade SOI process, with very low area and power, would be of clear practical interest for high-temperature sensing and instrumentation. The paper is commendable for reporting measurements on five samples, presenting mean and ±3σ curves, and including a comparison with prior high-temperature ADCs. The claimed FoM and area overhead are also noteworthy. However, the strength of the claims is limited by the power inconsistency, the absence of steady-state/lifetime validation at 250 °C, and the lack of a baseline chip without the mitigation circuits.

major comments (4)
  1. [Abstract, Conclusions, Table I] There is a factor-of-1000 inconsistency in the reported power consumption. The abstract and the Conclusions state 44 mW, while Table I lists 0.044 mW. The stated Schreier FoM of 140 dB is consistent only with 0.044 mW (44 µW) for the reported bandwidth of 0.146 kHz and SINAD of 74.5 dB. Because power is a headline result and enters the FoM calculation, all instances must be harmonized and the value verified; the authors should also specify exactly which supply domains are included (e.g., 1.8 V analog core only, or also 3.3 V I/O and reference).
  2. [Section IV, Fig. 6, Abstract] The claim that the ADC "operates up to 250 °C" and offers "reliable operation" is stronger than the evidence presented. The measurements in Fig. 6 appear to be snapshot temperature steps: no dwell time at each setpoint, no time-resolved data at 250 °C, and no thermal-cycling or soak data are reported. Since the process and PDK are qualified only to 175 °C, the 250 °C result rests entirely on these snapshots. The authors should either add steady-state/cycling validation or explicitly limit the claims to "functional operation at 250 °C during the described measurements" and remove "reliable operation" from the abstract and conclusions.
  3. [Section II.B, Fig. 3] The effectiveness of the leakage-compensation and clock-boosting techniques is demonstrated only by simulations that the paper itself says are "strictly reliable only up to the qualification temperature (175 °C)" (Section II.B). No measured comparison is provided with a baseline ADC fabricated without these mitigation circuits, so the experimental evidence that these techniques are what enables operation at 250 °C is indirect. The authors should state this limitation explicitly and, if possible, provide a measured comparison or per-block measurements.
  4. [Section IV, Fig. 6] Reporting only mean and ±3σ curves for five samples, without raw data or per-sample tables, limits verification of the central measurement result. With n=5, the ±3σ spread is itself a statistical estimate, and the paper does not state the number of repeated measurements per temperature point or the measurement uncertainty. Numerical data points or a table of per-sample SNR, SINAD, INL, and supply current at each temperature should be provided.
minor comments (6)
  1. [Fig. 6(d) caption] The units of the supply-current axis are not stated; please specify whether the current is per sample or averaged, and give the unit (e.g., µA).
  2. [Section IV] The text uses "integrative non-linearity" and "adsorbed"; these should be "integral non-linearity" and "drawn" or "consumed."
  3. [Section IV] There is a typo, "Schereier", which should be "Schreier."
  4. [Section IV, INL statement] The statement that INL is "below 1 mV" from -40 °C to 250 °C needs context: for a 1.8 V reference, 1 mV corresponds to about 2.3 LSB at 12 bits. Please explain how this coexists with a 12-bit ENOB (e.g., INL after calibration, different full-scale definition, or DC INL not directly limiting AC SINAD).
  5. [Reference list] Reference [30] has a typo in the URL: "hhttps://" should be "https://".
  6. [Section II, FoM definition] The Schreier FoM formula is given as SINAD + 10×log(BW/P); please explicitly state that P is in watts and BW in hertz, and note the unit convention used in Table I.

Circularity Check

0 steps flagged · score 0.0 of 10

No circular derivation: the headline SNR/SINAD/ENOB/FoM are direct measurements on five fabricated samples, not fitted inputs or outputs of a self-cited model.

full rationale

The paper's central claims are experimental: SNR above 93 dB, SINAD 74.5 dB, ENOB 12 and Schreier FoM 140 dB at 250 °C are computed from bitstream spectra and supply-current measurements at temperature setpoints (Section IV, Fig. 6, Table I). The FoM uses the standard definition SINAD + 10 log(BW/P) applied to measured quantities, so no fitted parameter is renamed as a prediction. The design section does rely on the authors' prior work [9] for high-temperature design criteria and for the extrapolated electromigration current-density rule, but that self-citation is not load-bearing for the headline result: the paper explicitly states that 'PDK simulations can not be trusted above this limit, and only accurate high-temperature measurements can confirm the expected behaviour of the circuit' (Section III), and the leakage-compensation simulations in Fig. 3(c)-(d) are presented only as trends, with the measured Fig. 6 data carrying the performance claim. The absence of soak or thermal-cycling data is a reliability-evidence limitation, not a circularity. No equation is defined in terms of the result it is supposed to establish, and no measurement is a fitted or self-cited input renamed as a prediction.

Assumptions & free parameters 2 free parameters · 4 assumptions · 0 invented entities

No new physical entities are introduced. The central claim rests on domain assumptions about the SOI process beyond its qualified range, the extrapolated effectiveness of leakage mitigation, and the representativeness of five samples. The design parameters listed are hand-chosen from simulations, not fitted to the measured ADC output.

free parameters (2)
  • Clock-boost voltage V_BST = 200 mV
    Chosen from simulation trade-off between channel leakage reduction and gate-oxide reliability (Fig. 3d); not fitted to the measured ADC output.
  • Dummy-transistor compensation mirror ratio = 4:1
    Chosen to estimate leakage from the large differential input pair; not independently calibrated by measurement in this paper.
assumptions (4)
  • domain assumption XT018 PDK models are reliable only up to 175 °C; behavior above 175 °C is extrapolated using trends from prior characterization [9].
    Section II and Section III state that PDK simulations cannot be trusted above the qualification temperature and that only measurements confirm behavior.
  • domain assumption Dummy-transistor junction leakage compensation and clock boosting remain effective at 250 °C.
    Section II.B shows effectiveness via simulations only up to 175 °C (Fig. 3c,d); no direct on-chip leakage measurement at 250 °C is presented.
  • domain assumption Electromigration threshold at 300 °C extrapolated from process specifications guides metal sizing.
    Section II.B sizes metal widths using a current density ten times below the extrapolated threshold, but no lifetime or electromigration test is reported.
  • domain assumption The five measured samples are representative of the fabrication process.
    Section IV reports statistics on five samples with no wafer, lot, or batch variation data.

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Cite this review

Pith. "Pith review of 12-bit Delta-Sigma ADC operating at a temperature of up to 250C in Standard 0.18 $\mu$m SOI CMOS." pith.science (2026). https://pith.science/paper/IPGBJVMA

@misc{pith2026250100482,
  author       = {Pith},
  title        = {Pith review of: 12-bit Delta-Sigma ADC operating at a temperature of up to 250C in Standard 0.18 $\mu$m SOI CMOS},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/IPGBJVMA}},
  note         = {Machine review of arXiv:2501.00482}
}
abstract

Some applications require electronic systems to operate at extremely high temperature. Extending the operating temperature range of automotive-grade CMOS processes -- through the use of dedicated design techniques -- can provide an important cost-effective advantage. We present a second-order discrete-time delta-sigma analog-to-digital converter operating at a temperature of up to 250 $^\circ$C, well beyond the 175 $^\circ$C qualification temperature of the automotive-grade CMOS process used for its fabrication (XFAB XT018). The analog-to-digital converter incorporates design techniques that are effective in mitigating the adverse effects of the high temperature, such as increased leakage currents and electromigration. We use configurations of dummy transistors for leakage compensation, clock-boosting methods to limit pass-gate cross-talk, and we optimized the circuit architecture to ensure stability and accuracy at high temperature. Comprehensive measurements demonstrate that the analog-to-digital converter achieves a signal-to-noise ratio exceeding 93 dB at 250 $^\circ$C, with an effective number of bits of 12, and a power consumption of only 44~mW. The die area of the converter is only 0.065~mm$^2$ and the area overhead of the high-temperature mitigation circuits is only 13.7%. The Schreier Figure of Merit is 140~dB at the maximum temperature of 250 $^\circ$C, proving the potential of the circuit for reliable operation in challenging applications such as gas and oil extraction and aeronautics.

Figures

Figures reproduced from arXiv: 2501.00482 by the authors.

Figure 1
Figure 1. Available ICs manufacturing technologies match the temperature [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. ADC architecture schematic overview: (a) 2 [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 4
Figure 4. Chip top view and layout magnification on the ADC block. [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗
Figures from the paper (3 more)
Figure 3
Figure 3. Figure 3: Design techniques for leakage current reduction: (a) Pass-gate [PITH_FULL_IMAGE:figures/full_fig_p004_3.png]
Figure 5
Figure 5. Figure 5: Measurement set-up for ADC characterization in the temperature [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]
Figure 6
Figure 6. Figure 6: Results from repeated measurements on five different ICs, performed at [PITH_FULL_IMAGE:figures/full_fig_p006_6.png]

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Pith tools

Reviewed August 10, 2026 · model on record in the stance chip above.