Towards a Cryogenic CMOS-Memristor Neural Decoder for Quantum Error Correction

Dominique Drouin; Linxiang Huang; Maher Benhouria; Patrick Dufour; Pierre-Antoine Mouny; Pooya Ronagh; Sophie Rochette; Victor Yon; Yann Beilliard

REVIEW 3 major objections 5 minor 8 references

Towards a Cryogenic CMOS-Memristor Neural Decoder for Quantum Error Correction

T0 review · 3 major / 5 minor · reviewed 2026-08-10 · deepseek-v4-flash

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Pith's one-line read The paper demonstrates a CMOS-memristor neural decoder ASIC that operates down to 1.2K, with stable activation shapes and pulse responses, laying groundwork for decoding quantum errors inside the cryostat.

desk verdict Useful cryo-CMOS characterization, but the headline claim about a CMOS-memristor decoder is untested—all tests ran with fixed resistors instead of memristors. read the letter →

arxiv 2501.14525 v1 pith:YKW5O6X4 submitted 2025-01-24 quant-ph cs.AR

Pierre-Antoine Mouny , Maher Benhouria , Victor Yon , Patrick Dufour , Linxiang Huang , Yann Beilliard , Sophie Rochette , Dominique Drouin

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Pooya Ronagh

This is my paper · ORCID

classification quant-phcs.AR

keywords cryogenicelectronicsmemristorcrossbarin-memorycomputingquantumerrorcorrectionneuraldecoderrecurrentnetworkanalogASICsurfacecode

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Quantum error correction produces syndrome data at rates that overwhelm cabling between a cryostat and room-temperature decoders; the paper's answer is to put a small neural decoder next to the qubits. It reports a 180nm CMOS ASIC whose recurrent neural network performs vector-matrix multiplications in memristor crossbars, with analog sigmoid activation, an analog current-memory recurrence loop, and a threshold output. Measured from 300K down to 1.2K, the chip shows stable sigmoid shapes and pulse responses and roughly constant power consumption (about 13-15mW), which the authors take as evidence that a scalable cryogenic decoder is feasible. In the electrical characterizations the memristors were replaced with fixed discrete resistors, so what is directly measured is the CMOS signal chain with ideal resistive weights; the cryogenic behavior of real memristors is carried by earlier programming results. The paper's claim is therefore that this architecture is the right foundation, with the memristor crossbar as the planned weight storage.

What carries the argument

The mechanism that carries the argument is in-memory computing with a memristor crossbar: each weight is encoded as the difference of two memristor conductances ($G_{ij}^{+}$ and $G_{ij}^{-}$), and by Kirchhoff's and Ohm's laws the output current on a column is $I_j^{\pm} = \sum_i G_{ij}^{\pm} V_i^{\mathrm{IN}}$, exactly the vector-matrix product needed for a neural layer. Around this core, the ASIC provides a current buffer with a subtractor to combine the differential currents, a resistive-circuit sigmoid activation whose voltage transfer depends on transistor thresholds, an analog current-memory cell that latches the recurrent current and releases it on a trigger, and a transimpedance amplifier plus comparator for the output layer. In the reported characterizations, the crossbar conductances were implemented by fixed resistors, so the measured sigmoid shapes and pulse responses test the CMOS periphery rather than the memristors themselves.

What would settle it

Replace the fixed resistors with a real memristor crossbar, program the same weight values at 4.2K, and run the 1μs input pulses at 1.2K; if the sigmoid outputs, recurrent memory, or final thresholded decision change when the memristors drift or show pulse-to-pulse variability, the claim that the CMOS-memristor decoder is viable at cryogenic temperature would be refuted.

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Extended reading notes

Core claim

The paper's central claim is that a recurrent neural network decoder for quantum error correction can be built as a small analog ASIC operating at cryogenic temperatures, with the network's weights held in metal-oxide memristor crossbars and all arithmetic done in the current domain. The chip implements an input layer (vector-matrix multiply plus sigmoid), a recurrent layer with an analog current-memory cell that stores the previous hidden state, and an output layer with a threshold comparison. Cryogenic characterization at 1.2K, 4.2K, 35K, and 77K shows that the sigmoid activation changes shape with temperature—sharper transition and larger slope at the lowest temperatures—while the final inference output remains unchanged in the tested configuration, and total power stays roughly constant at about 13-15mW. The authors are explicit that, for the electrical measurements reported here, the memristors were replaced by fixed discrete resistors, so the demonstrated stability belongs to the CMOS analog circuits; the memristor crossbar's own cryogenic programmability is cited from prior work. Taken together, the paper claims this validates the viability of a CMOS-memristor decoder and identifies the scaling path (smaller CMOS nodes) to reach the watt-level budget of a dilution refrigerator.

Load-bearing premise

The experiments that show the decoder working at 1.2K used ordinary fixed resistors in place of the memristors, so everything depends on real memristors, once programmed at cryogenic temperature, behaving enough like those ideal resistors to keep the same inference results.

Editorial extensions

If this is right

A decoder co-located with the qubits avoids routing gigabytes of syndrome data per second out of the cryostat, removing a central scalability bottleneck for quantum error correction.
The recurrent analog memory lets the decoder handle temporal syndrome streams without repeatedly fetching state from cryogenic memory, cutting data movement.
The chip's power draw stays near 13-15mW from 300K down to 1.2K, so the CMOS signal chain itself is not the power barrier; the authors identify smaller technology nodes as the route to a fridge-compatible decoder.
Temperature-dependent sigmoid changes did not flip the inference result in the tested configuration, suggesting hardware-aware training can tolerate cryogenic device shifts.
This is a proof-of-concept scale; the input and recurrent layers must be scaled up before the decoder can correct errors on large surface codes.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

A decisive follow-up the paper does not run is to repeat the same measurements with an actual cryogenically programmed memristor crossbar; the fixed-resistor results cannot bound the effect of memristor conductance drift or cycle-to-cycle variability on the decoder output.
The sharper sigmoid at 1.2K might improve the separation between the two output classes, potentially relaxing the output comparator's threshold margin—a design lever the authors do not discuss.
The power breakdown suggests the 3.3V supply dominates; before projecting node-shrink gains, it would be useful to separate analog-core power from pad and I/O power, which scale differently.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Good that you sent this one. Quick take: it's a solid preliminary hardware characterization of a 180nm CMOS analog RNN chip at 1.2K, but the central claim in the abstract overreaches. Every electrical test described in Section III replaces the memristors with fixed discrete resistors. So we learn that the CMOS front end—current buffers, sigmoid circuit, current memory, TIA—works at cryogenic temperatures, which is genuinely useful data. We do not learn that a memristor-based decoder works at 1.2K. The conductance range, programming nonlinearity, variability, and sneak-path behavior of real memristors are absent. That's the main soft spot, and it's load-bearing.

The second issue is the abstract's 'stable activation function shapes and pulse responses.' The paper's own Fig. 9 and 10, and the Discussion, show temperature-dependent sigmoid behavior: sharper transition at 1.2K and 4.2K, and no output pulse for Sigmoid_2 at 4.2K. The authors are honest about this in Section V, so it's not hidden, but the abstract contradicts it. That needs fixing.

What's new and good: the fabricated ASIC itself, the cryogenic data down to 1.2K on the analog building blocks, and the power table (13-15mW for this scale). The paper also states plainly that this power is not compatible with substantial scaling and suggests smaller technology nodes. I appreciate that candor. The recurrence pulse response at room temperature and the comparison with Spectre simulations give a useful baseline.

Soft spots beyond the memristor substitution: the dynamic cryogenic test used only one input configuration (VIN1=VIN2=2.5V), so the pulse-response comparison across temperatures is thin. The conclusion also says 'stable performance down to 1.2K' which again glosses over the Sigmoid_2 dropout. None of this makes the paper worthless; it just doesn't support the system-level claim.

Who's it for? People working on cryogenic control electronics for quantum computers, especially analog neural decoders. They'll want to know that the CMOS front end can survive 1.2K and where the temperature sensitivities are. The citation pattern is fine—self-citations are to their own prior work on the memristive decoder and cryogenic memristor programming, which is the natural lineage.

Recommendation: send it to peer review, but with a required revision. The authors should either (a) characterize the ASIC with real memristors in the loop, or at minimum (b) recalibrate the abstract and conclusion to claim only 'cryogenic characterization of the CMOS analog front end' and explicitly flag the fixed-resistor substitution as the key limitation. As is, it's a credible progress report, not a demonstration of the full decoder.

Referee Report

3 major / 5 minor

Summary. The paper reports a small-scale ASIC intended as a CMOS-memristor neural decoder for quantum error correction. The architecture uses an input vector-matrix multiplication stage, an analog sigmoid activation, a recurrent layer with analog current memory, and an output layer with a threshold activation. The authors fabricated the chip in 180nm CMOS, built a PCB test platform, and performed DC and pulse measurements at room temperature and at cryogenic temperatures down to 1.2K. They report sigmoid shapes, pulse responses, and power consumption. The manuscript explicitly states that, for all electrical characterizations, the memristors were replaced with fixed discrete resistors, so the reported measurements characterize the CMOS analog signal chain with a resistor crossbar, not the full CMOS-memristor system. The abstract and conclusion nevertheless claim stable activation function shapes and stable performance down to 1.2K, and the paper presents the work as laying the foundation for scalable CMOS-memristor neural decoders.

Significance. The paper addresses an important practical problem: the wiring and power bottleneck for quantum error correction decoders at cryogenic temperatures. The experimental effort is substantial: a custom 180nm CMOS ASIC was designed and tested in a cryostat, including a careful room-temperature comparison with Cadence Spectre simulations and power consumption measurements at several temperatures. A notable strength is the honest disclosure in Section III that the memristors were replaced with fixed resistors for all characterizations; this makes the limitations of the current evidence visible. If the authors subsequently validate the full CMOS-memristor integration at cryogenic temperatures, the analog front-end characterization reported here would be a useful building block. At present, however, the data do not support the central claim that a CMOS-memristor neural decoder operates at 1.2K, because no measurement involving an actual memristor is reported and the activation-function stability claim is contradicted by the paper's own discussion.

major comments (3)

[Section III, Figs. 7–10] Every electrical characterization in the paper used fixed discrete resistors instead of memristors. Section III states, 'For the following electrical characterizations, memristors were replaced with fixed discrete resistors.' Consequently, Figs. 7–10 measure the CMOS signal chain with ideal linear resistors, not the proposed CMOS-memristor decoder. No evidence is presented that cryogenically programmed metal-oxide memristors of the type in ref. [9] have conductances within the ASIC input range, that their programming variability is compatible with the current buffer, or that their pulse response matches the fixed resistors. The abstract's claim of 'stable activation function shapes and pulse responses at cryogenic temperatures' therefore applies only to a resistor-loaded test circuit, and the title's 'CMOS-Memristor Neural Decoder' overstates what was demonstrated.
[Section V, Figs. 9 and 10] The abstract and conclusion claim stable activation function shapes and stable performance down to 1.2K, but Section V reports that the sigmoid shape depends on temperature: at 1.2K and 4.2K the transition is sharper, the linear-regime slope is larger, and at 4.2K Sigmoid_2 produces no output pulse. These observations directly contradict the stability claim. The statement that 'the neural network output is unchanged with temperature' is based on a single input configuration and does not restore the claim, since no end-to-end decoding accuracy or error-correction performance is reported. The abstract and conclusion should be revised to reflect the actual temperature-dependent behavior shown in the data.
[Section IV-B, Table I] The cryogenic pulse tests use a single set of inputs (VIN1=VIN2=2.5V) and a single resistance configuration, and the characterization is performed on one sample (Section IV-A mentions 'one sample'). The power measurements in Table I show 13.4–15.3 mW total power, and Section V acknowledges that the power consumption is 'not compatible with a substantial scaling' of the architecture. The conclusion's statement that the results indicate 'potential scalability and reliability in cryogenic environments' is therefore unsupported by the presented measurements, which contain no scaling analysis, no reliability statistics, and no error-correction performance metric. The scope of the claims should be limited to what the data demonstrate: a preliminary cryogenic characterization of the CMOS analog blocks with a resistive crossbar.

minor comments (5)

[Author affiliations] The email address in the author affiliation contains a typo: 'irrersible.tech' should be 'irreversible.tech'.
[Section II, Eq. (1)] The inline equation for the vector-matrix multiplication appears corrupted in the text: '𝐼_𝑗^± = 𝑖 Σ 𝐺𝑖𝑗^± 𝑉𝑖^𝐼𝑁' lacks a proper summation notation with index and bounds, and should be typeset as a numbered display equation.
[Fig. 10] The axis labels and units are missing from the cryogenic pulse-response figure, making it difficult to compare output amplitudes and pulse widths across temperatures.
[Section III-B] The sentence describing the cryostat stages reads 'the 4K-pot and 50K-stage are kept at 3.2K respectively 60K'; this should be rephrased to 'kept at 3.2K and 60K, respectively' for clarity.
[Section V] The discussion of the temperature dependence of the sigmoid would benefit from a quantitative statement of the observed slope change and output amplitude reduction, rather than only a qualitative description.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the paper is an experimental characterization, and its measurements are not derived from the claims by construction; the fixed-resistor substitution is a scope/validity limitation, not a circular step.

full rationale

This is an experimental hardware paper, not a derivation, so there is no equation-level circularity to expose. The few citations to the authors' own prior work (Refs. [8] and [9]) provide background premises about the RNN decoder architecture and about cryogenic memristor programming; those prior results are empirical, published, and externally falsifiable, and they are not constructed within this paper to force the conclusion. The most notable issue is that Section III states: "For the following electrical characterizations, memristors were replaced with fixed discrete resistors." This means the measured sigmoid shapes, pulse responses, and power figures characterize the CMOS circuit loaded with ideal resistors, not the full CMOS-memristor system claimed in the abstract. That is a real scoping/overclaim concern, but it is not circularity: the measured data are not made equal to the system-level claim by definition, no fitted parameter is relabeled as a prediction, no uniqueness theorem is imported, and no result reduces to its own input. Accordingly, the paper does not exhibit a circular derivation chain.

Assumptions & free parameters 0 free parameters · 3 assumptions · 0 invented entities

The main load-bearing axiom is the substitution of ideal resistors for memristors. The paper explicitly discloses this substitution, but it means the measurements do not test the claimed memristor-based system. The cryogenic compatibility of memristors themselves is imported from prior work by the same group.

assumptions (3)

ad hoc to paper Fixed discrete resistors faithfully represent programmed memristor conductances in the crossbar.
All electrical characterizations replaced memristors with fixed resistors (Section III), and the paper does not validate that real memristors produce the same sigmoid and pulse behavior.
domain assumption Memristors are cryogenically programmable and stable down to 4.2K.
Taken from reference [9], a prior paper by some of the same authors; the current paper does not perform memristor programming at 1.2K.
domain assumption CMOS analog building blocks (sigmoid, current memory, TIA) operate correctly at 1.2K with the observed deviations.
The paper infers correctness from qualitative pulse shapes; no end-to-end decoding accuracy is measured.

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Cite this review

Pith. "Pith review of Towards a Cryogenic CMOS-Memristor Neural Decoder for Quantum Error Correction." pith.science (2026). https://pith.science/paper/YKW5O6X4

@misc{pith2026250114525,
  author       = {Pith},
  title        = {Pith review of: Towards a Cryogenic CMOS-Memristor Neural Decoder for Quantum Error Correction},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/YKW5O6X4}},
  note         = {Machine review of arXiv:2501.14525}
}

read the original abstract

This paper presents a novel approach utilizing a scalable neural decoder application-specific integrated circuit (ASIC) based on metal oxide memristors in a 180nm CMOS technology. The ASIC architecture employs in-memory computing with memristor crossbars for efficient vector-matrix multiplications (VMM). The ASIC decoder architecture includes an input layer implemented with a VMM and an analog sigmoid activation function, a recurrent layer with analog memory, and an output layer with a VMM and a threshold activation function. Cryogenic characterization of the ASIC is conducted, demonstrating its performance at both room temperature and cryogenic temperatures down to 1.2K. Results indicate stable activation function shapes and pulse responses at cryogenic temperatures. Moreover, power consumption measurements reveal consistent behavior at room and cryogenic temperatures. Overall, this study lays the foundation for developing efficient and scalable neural decoders for quantum error correction in cryogenic environments.

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

8 extracted references · 4 canonical work pages

[9]

Mouny, P.-A., Dawant, R., Galaup, B., Ecoffey, S., Pioro-Ladrière, M., Beilliard, Y., & Drouin, D. (2023). Analog programming of CMOS-compatible Al 2 O 3 /TiO 2−x memristor at 4.2 K after metal-insulator transition suppression by cryogenic reforming. In Applied Physics Letters (Vol. 123, Issue 16). AIP Publishing. https://doi.org/10.1063/5.0170058 [10] Ki...

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Pith tools

Reviewed August 10, 2026 · model on record in the stance chip above.

[1] [9]

Mouny, P.-A., Dawant, R., Galaup, B., Ecoffey, S., Pioro-Ladrière, M., Beilliard, Y., & Drouin, D. (2023). Analog programming of CMOS-compatible Al 2 O 3 /TiO 2−x memristor at 4.2 K after metal-insulator transition suppression by cryogenic reforming. In Applied Physics Letters (Vol. 123, Issue 16). AIP Publishing. https://doi.org/10.1063/5.0170058 [10] Ki...

work page arXiv 2023

[2] [1]

G., Mariantoni, M., Martinis, J

Fowler, A. G., Mariantoni, M., Martinis, J. M., & Cleland, A. N. (2012). Surface codes: Towards practical large-scale quantum computation. In Physical Review A (Vol. 86, Issue 3). American Physical Society (APS). https://doi.org/10.1103/physreva.86.032324

doi:10.1103/physreva.86.032324 2012

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R., Pasandi, G., Ding, Y., Pedram, M., & Chong, F

Holmes, A., Jokar, M. R., Pasandi, G., Ding, Y., Pedram, M., & Chong, F. T. (2020). NISQ+: Boosting quantum computing power by approximating quantum error correction. In 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA). 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA). IEEE. https://doi.org...

arXiv 2020

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Ueno, Y., Kondo, M., Tanaka, M., Suzuki, Y., & Tabuchi, Y. (2021). QECOOL: On-Line Quantum Error Correction with a Superconducting Decoder for Surface Code. In 2021 58th ACM/IEEE Design Automation Conference (DAC). 2021 58th ACM/IEEE Design Automation Conference (DAC). IEEE. https://doi.org/10.1109/dac18074.2021.9586326 [4] Liyanage, N., Wu, Y., Deters, A...

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M., Bialas, T., Buğdaycı, O., Campbell, E

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Homulle, H. (2019). Cryogenic electronics for the read-out of quantum processors. https://doi.org/10.4233/uuid:e833f394-c8b1-46e2-86b8-da0c71559538

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