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REVIEW 4 major objections 4 minor 45 references

Gate teleportation-assisted routing for quantum algorithms

T0 review · 4 major / 4 minor · reviewed 2026-08-08 · deepseek-v4-flash

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Pith's one-line read By routing two-qubit gates through teleportation paths on idle auxiliary qubits, the proposed RTG method reduces circuit depth by 10-25% on selected benchmarks over standard SWAP-based routing.

desk verdict Useful incremental routing heuristic with an honest implementation study, but the abstract's 10–25% reduction is not supported by the paper's own tables and the timing model needs justification. read the letter →

arxiv 2502.04138 v2 pith:STY3PRIQ submitted 2025-02-06 quant-ph

Aravind Plathanam Babu , Oskari Kerppo , Andrés Muñoz Moller , Majid Haghparast , Matti Silveri This is my paper · ORCID
classification quant-ph MSC 81P68 PACS 03.67.Lx
keywords quantumroutinggateteleportationcircuitdepthqubitmappingdynamiccircuitsheavy-hextopologyQAOADeutsch-Jozsa
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper proposes a qubit routing method that uses gate teleportation instead of SWAP chains to execute two-qubit gates between non-adjacent qubits. It claims that by threading teleportation paths through idle auxiliary qubits on a fixed hardware topology, and selecting those paths with a heuristic search, circuit depth can be reduced by 10-25% on selected benchmark circuits compared to standard SWAP-based routing. The method is demonstrated for CNOT teleportation on the Deutsch-Jozsa algorithm and controlled-U teleportation on QAOA over a heavy-hex topology segment. A noise-aware variant weighs teleportation error against depth savings. The practical payoff would be shallower circuits and less decoherence on near-term processors without changing the native gate set.

What carries the argument

The central object is the virtual edge: a path through idle auxiliary qubits on the coupling map that implements a long-distance CNOT or controlled-U gate via mid-circuit measurements and feed-forward, with a teleportation circuit whose depth is claimed to be independent of path length. The heuristic search evaluates subsets of such virtual edges by transpiling with SABRE, estimating temporal depth from Eq. (1) with t_tele = 3 t2q, and, in the noise-aware variant, estimating two-qubit error cost from Eq. (2), then keeps the subset that minimizes both metrics.

What would settle it

A direct hardware measurement of teleported CNOT execution time, including mid-circuit measurement and feed-forward latency, as a function of path length on a heavy-hex device would settle the claim: if the observed temporal depth grows with N or exceeds three native two-qubit gate times even for short paths, the depth-reduction model is invalid. Alternatively, running the paper's benchmarks on hardware and comparing end-to-end circuit depths with and without teleportation would falsify the claim if the reductions fall outside the stated 10-25% range.

Watch

Extended reading notes

Core claim

The central claim is that gate teleportation can serve as a routing primitive that complements SWAP-based routing, and that a greedy heuristic over virtual connections can select which gates to teleport so that temporal circuit depth decreases. On 15-qubit benchmarks including Deutsch-Jozsa, graph state preparation, QFT, and QAOA, the RTG method achieves depth reductions of roughly 10-25% over a line layout routed with the standard SWAP-based method SABRE. When the full teleportation circuits are inserted, the depth reduction shrinks but remains positive, because teleported gates add CNOTs on auxiliary qubits but keep the number of CNOTs on data qubits comparable to the baseline. The paper also shows that teleporting RZZ gates via controlled-U teleportation, rather than decomposing them into CNOTs before teleporting, is the better choice for QAOA circuits.

Load-bearing premise

The central load-bearing premise is that a teleported two-qubit gate has a fixed temporal cost of three native two-qubit gates and a depth independent of the number of auxiliary qubits in the path; if teleportation depth actually grows with path length or if measurement and feed-forward latency dominates, the reported 10-25% depth reductions could shrink or disappear.

Editorial extensions

If this is right

  • RTG reduces temporal depth for circuits with sparse non-local two-qubit gates, at the cost of extra CNOTs on auxiliary qubits.
  • Teleporting controlled-U or RZZ gates is preferable to teleporting decomposed CNOTs in circuits such as QAOA.
  • Depth reduction is structure-dependent: graph state and QFT benchmarks lose some benefit when noise-aware selection is used.
  • Noise-aware RTG can trade depth savings against error cost, potentially improving circuit reliability on noisy hardware.
  • The method requires hardware with mid-circuit measurement and feed-forward capability, as well as idle auxiliary qubits to act as teleportation paths.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If mid-circuit measurement and feed-forward latencies improve relative to two-qubit gate times, teleportation-assisted routing could become competitive for shorter paths and repeated gates, widening the depth-reduction window beyond 25%.
  • The heuristic's restriction against reusing teleportation paths is a proxy for error accumulation; an explicit model of reset and error costs per reuse could change which gates are selected for teleportation.
  • The constant-depth teleportation model implies that the method's advantage should grow on topologies where native two-qubit gates are slow relative to measurements, a testable comparative prediction across hardware generations.
  • The search over virtual edges grows combinatorially with auxiliary qubit count; whether the greedy heuristic stays near optimal on larger, denser topologies is an open question that could be probed by exact search on small instances.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 4 minor

Summary. The paper proposes Routing with Teleported Gates (RTG), a method that augments SWAP-based qubit routing with gate teleportation over auxiliary qubits in a fixed superconducting topology. It defines a temporal-depth cost model, a heuristic search over virtual connections, and a noise-aware variant, then benchmarks on 15-qubit circuits from MQT Bench on a heavy-hex topology. The paper reports depth reductions of 10–25% compared with a line-topology baseline, with case studies on Deutsch–Jozsa and QAOA circuits.

Significance. Gate-teleportation-assisted routing is a timely and plausible idea given that dynamic circuits with mid-circuit measurement and feed-forward are available on current processors. The paper gives a concrete algorithmic framework, integrates with SABRE, and includes implementation-level tables that honestly expose the overhead of teleportation circuits. However, the central quantitative claim is not yet robust: the temporal-depth model relies on an unvalidated teleported-gate time, several implementation results fall below the abstract's claimed range, and the baseline is a hand-picked line layout rather than an optimized standard-routing baseline. With a justified timing model and corrected claims, the work would be a useful contribution to routing for near-term hardware.

major comments (4)
  1. [Section 2, Eq. (1)] The temporal-depth model assigns t_tele^g = 3 t_2q^g and the text asserts that the depth of teleportation circuits is constant regardless of distance N, but no derivation or device timing model is provided. A teleported-CNOT layer involves N mid-circuit measurements and N+1 CNOTs; even if the ideal gate-level depth is O(1), wall-clock time is likely dominated by measurement, reset, and feed-forward latency. Since Eq. (1) is the objective minimized by RTG and is used for Tables 1–2 and Fig. 5, an overoptimistic t_tele inflates every reported reduction. The paper should either derive t_tele from a concrete timing model or show that the reported reductions survive a sensitivity analysis over t_tele in a plausible range (e.g., 3–50 t_2q).
  2. [Abstract and Tables 1–2] The abstract claims a 10–25% depth reduction, and the conclusions state 10–20%, but the implementation-level reductions in Tables 1 and 2 are 11%, 10%, 16%, 19%, 12%, 16%, 7% for Deutsch–Jozsa and 11%, 4%, 25%, 19%, 9%, 13%, 24% for QAOA. Several values fall below the abstract's lower bound, including 7% for 15-qubit Deutsch–Jozsa and 4% for 10-qubit QAOA. The headline range should be revised to match the data, or the abstract should specify that the range refers only to the idealized virtual-connection results in Fig. 5.
  3. [Sections 3.1–3.3] The baseline is a hand-picked line topology (qubits 18–32) rather than a SABRE-optimized layout on the heavy-hex graph. The authors acknowledge that 'this particular layout is a trivial choice,' but the abstract's comparison is to 'regular routing without using teleported gates,' which in practice would use a better initial layout. If the baseline is deliberately unfavorable, the depth reductions are not a fair measure of improvement over standard routing. Please compare against SABRE with its own layout optimization and/or against native heavy-hex routing without teleportation, and report reductions relative to that baseline.
  4. [Tables 1–2 and Sec. 3.2–3.3] The gap between the 'virtual c. map' (idealized) and 'virtual c. map (Impl.)' columns is large and not fully explained: for example, Deutsch–Jozsa at 15 qubits has an expected reduction of 15% but an implemented reduction of 7%, and QAOA at 10 qubits has 23% expected but 4% implemented. The paper should treat the implementation numbers as the primary result and discuss why the teleportation overhead erodes the expected gain so substantially, since this directly affects the practical relevance of the method.
minor comments (4)
  1. [Fig. 5] The reported depth-reduction percentages appear to be single values from randomized transpilation; please report statistics (mean, min, max) over the multiple random seeds used by the RTG search, or state that only one representative trial is shown.
  2. [Eq. (1)] The notation N_L^{1q}, N_L^{2q}, and N_L^tele is not fully defined: clarify how a layer containing both a native two-qubit gate and a teleported two-qubit gate is counted, and whether single-qubit layers are counted separately.
  3. [Sec. 3.1] The sentence 'The results demonstrate a reduction in circuit depth across all cases except for QAOA' is important and should be reflected in the abstract; as written, the abstract implies the 10–25% range covers all selected algorithms.
  4. [Acknowledgements] There is a minor typo: 'Grants No. 8582/31/2022 and 8436/31/2022,,' contains a double comma.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the reported depth reductions are obtained from an explicit cost model, external teleportation protocols, and independent benchmark circuits, not from the paper's own conclusions.

full rationale

The RTG method is an optimization procedure over a cost function, Eq. (1), with parameters t_tele = 3t2q and P_tele = 10P2q that are stated as expected future device values, not fitted to the reported outcomes. The teleportation protocols themselves are imported from independent references ([33], [39]), and the benchmark circuits and baseline transpilation come from MQT Bench ([41]) and SABRE ([10]); none of these are the authors' own prior claims. The paper's Tables 1 and 2 report circuit depth after actually substituting the teleportation circuits (step 8 of Fig. 3) against a SABRE line-map baseline, so the reductions are internal comparisons of the same transpiler with and without virtual edges. Eq. (2) is likewise a stated error-cost model. No step in the derivation defines its target in terms of itself, fits a parameter to a subset and then predicts that subset, or invokes a uniqueness theorem from the authors' previous work. The principal weakness is substantive rather than circular: the magnitude of the claimed 10-25% reduction depends on the assumed constant-depth teleportation circuits and on t_tele = 3t2q (and the abstract's range already exceeds some tabulated implementation-level values, e.g., 7% and 4%). Those are modeling-sensitivity concerns, not circularity, because they concern whether the assumed inputs are true, not whether the outputs are derived from them.

Assumptions & free parameters 4 free parameters · 4 assumptions · 0 invented entities

The main resourcing choices are the assumed teleported gate time/error and the heuristic search hyperparameters; no new physical entities are introduced.

free parameters (4)
  • Teleported gate execution time (t_tele) = 3 * t2q (assumed)
    Used in Eq. (1) to compute temporal depth; not measured, chosen as an optimistic estimate for future devices (Sec. 3.1).
  • Teleported gate error probability (P_tele) = 10 * P2q (assumed)
    Used in Eq. (2) for error cost; authors note current devices have P_tele about 100 * P2q, so this value is optimistic and affects the noise-aware selection (Sec. 3.1).
  • Repeat limit for teleportation paths = not specified (e.g., at most 2 uses)
    Heuristic search prunes connections used too often; the exact limit is not stated, so it is a free choice affecting results (Sec. 2, step 4).
  • QAOA virtual connections = qubits 20-28 and 22-30
    For the QAOA case study, two fixed connections are chosen by hand for all qubit counts, and they are not optimized per case (Sec. 3.3).
assumptions (4)
  • domain assumption Standard gate teleportation protocol for CNOT and controlled-U gates
    Assumed correct and applicable to the heavy-hex topology with mid-circuit measurements (Sec. 2, Ref. [28,33]).
  • ad hoc to paper Teleportation circuits have constant depth independent of path length N
    Stated in Sec. 2 without proof; the depth of preparing auxiliary entanglement may scale with N on a line.
  • domain assumption Temporal depth formula Eq. (1) accurately captures runtime
    Assumes fixed gate times and ignores measurement/feed-forward latency and layer counting ambiguity for mixed layers (Sec. 2, Eq. 1).
  • domain assumption Two-qubit error model Eq. (2) captures dominant errors
    Ignores single-qubit errors, measurement errors, resets, and crosstalk (Sec. 2, Eq. 2).

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Cite this review

Pith. "Pith review of Gate teleportation-assisted routing for quantum algorithms." pith.science (2026). https://pith.science/paper/STY3PRIQ

@misc{pith2026250204138,
  author       = {Pith},
  title        = {Pith review of: Gate teleportation-assisted routing for quantum algorithms},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/STY3PRIQ}},
  note         = {Machine review of arXiv:2502.04138}
}
abstract

The limited qubit connectivity of quantum processors poses a significant challenge in deploying practical algorithms and logical gates, necessitating efficient qubit mapping and routing strategies. When implementing a gate that requires additional connectivity beyond the native connectivity, the qubit state must be moved to a nearby connected qubit to execute the desired gate locally. This is typically achieved using a series of SWAP gates creating a SWAP path. However, routing methods relying on SWAP gates often lead to increased circuit depth and gate count, motivating the need for alternative approaches. This work explores the potential of teleported gates to improve qubit routing efficiency, focusing on implementation within specific hardware topologies and benchmark quantum algorithms. We propose a routing method that is assisted by gate teleportation. It establishes additional connectivity using gate teleportation paths through available unused qubits, termed auxiliary qubits, within the topology. To optimize this approach, we have developed an algorithm to identify the best gate teleportation connections, considering their potential to reduce the depth of the circuit and address possible errors that may arise from the teleportation paths. Finally, we demonstrate depth reduction with gate teleportation-assisted routing in various benchmark algorithms, including case studies on the compilation of the Deutsch-Jozsa algorithm and the Quantum Approximation Optimization Algorithm (QAOA) for heavy-hexagon topology used in IBM 127-qubit Eagle r3 processors. Our benchmark results show a 10-25 $\%$ depth reduction in the routing of selected algorithms compared to regular routing without using the teleported gate.

Figures

Figures reproduced from arXiv: 2502.04138 by the authors.

Figure 1
Figure 1. Circuit diagram schematic of a gate-teleportation implementation of a long [PITH_FULL_IMAGE:figures/full_fig_p005_1.png] view at source ↗
Figure 2
Figure 2. Circuit diagram schematic of a gate-teleportation implementation of a long [PITH_FULL_IMAGE:figures/full_fig_p006_2.png] view at source ↗
Figure 3
Figure 3. Flowchart representing the implementation of noise-aware Routing with [PITH_FULL_IMAGE:figures/full_fig_p008_3.png] view at source ↗
Figures from the paper (2 more)
Figure 4
Figure 4. Figure 4: (a) A section of the IBM 127-qubit Eagle r3 processor topology [ [PITH_FULL_IMAGE:figures/full_fig_p009_4.png]
Figure 5
Figure 5. Figure 5: The percentage of depth reduction achieved compared to the initial line [PITH_FULL_IMAGE:figures/full_fig_p010_5.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

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