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REVIEW 3 major objections 5 minor 29 references

New Security Challenges Towards In-Sensor Computing Systems

T0 review · 3 major / 5 minor · reviewed 2026-08-08 · deepseek-v4-flash

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Pith's one-line read This paper claims that in-sensor computing systems, by fusing sensing and computation, create new hardware security threats at board, chip, and device levels that existing digital defenses cannot catch.

desk verdict A useful first security taxonomy for in-sensor computing, but the two demos overclaim what they prove; the qualitative analysis deserves a referee. read the letter →

arxiv 2502.05046 v1 pith:KDFRY3MD submitted 2025-02-07 cs.CR cs.AR

Mashrafi Kajol , Qiaoyan Yu This is my paper · ORCID
classification cs.CRcs.AR
keywords in-sensorcomputinghardwaresecurityfaultattackcounterfeitanalogside-channelhealthmonitoring3Dintegrationenvironmentalinterference
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

In-sensor computing (ISC) puts sensing, memory, and computation in one compact unit so data are processed where they are collected, saving energy and latency for health monitors and wearables. This paper sets out to establish that this fusion creates a hardware-security problem that cannot be handled by extending traditional sensor-involved computing (TSC) defenses: the same compaction removes the probing points, digitization steps, and interface boundaries that existing security tools rely on. Claiming to be the first security analysis of ISC systems, it compares attack accessibility, prior knowledge, tools, and detection difficulty between TSC and ISC, and it predicts new attack scenarios at the board, chip, and device levels. Two proof-of-concept demos ground the claims: a counterfeit material in a ferroelectric biosensor flips a biomolecule-detection output, and a low-cost light-controlled circuit on a sensor data bus changes an emotion-classification conclusion. The paper's point is that security must be designed into the material and device phase of ISC, not bolted on afterward.

What carries the argument

The central object is a three-level attack-surface decomposition of ISC systems — board, chip, and device — keyed to how sensing and computation are integrated. At each level the paper identifies what an attacker must know and what tools are needed: board-level attacks exploit the analog link between sensor and computation and the sensor's sensitivity to its environment; chip-level attacks target vertical interconnects and untrusted 3D-integration entities; device-level attacks require full understanding of the sensing material and are the hardest to detect. A comparison table against traditional sensor-involved computing carries the argument that ISC trades easier access for harder detection. The demos provide the physical anchors: a double-gate ferroelectric tunnel FET gustatory sensor shows a counterfeit-oxide-induced shift in the current-voltage characteristic that produces a wrong recognition output, and an optical sensor wired to an external classification model shows light-induced interference flipping the predicted emotion.

What would settle it

Replace the external classifier in Demo 2 with an in-sensor implementation of the same emotion-recognition function, keep the same low-cost light-controlled circuit, and compare output labels under identical illumination. If the label does not flip, the demo does not establish the board-level ISC attack.

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Extended reading notes

Core claim

On its own terms, the paper's central claim is that in-sensor computing systems have a distinct security profile: compared with traditional sensor-involved computing, ISC reduces remote accessibility but demands more attacker knowledge, more customized tools, and makes attacks harder to detect. Because an ISC system's sensing and computing behavior is fixed by material properties and device mechanisms, the design and modeling stage becomes security-critical; a malicious foundry can tamper with both analog and digital parts, and counterfeit materials can shift device characteristics in ways that surface only after full data processing. At board level, environmental interference and analog-format side channels attack sensor data before digitization; at chip level, 3D-stacked interconnects create new fault-injection points; at device level, customized counterfeit attacks need full sensor knowledge and are hard to diagnose for lack of probing locations. The two demos are offered as evidence that these attacks are physically realizable and as starting points for countermeasure design.

Load-bearing premise

The second demo's setup is a conventional sensor plus external classifier, not a true in-sensor computing system; the paper's board-level attack claim rests on the assumption that the observed interference transfers to systems where computation happens inside the sensor.

Editorial extensions

If this is right

  • If the paper's analysis is right, ISC design flows must treat the material and device modeling phase as a security stage, because a tampered material changes every result the device will ever produce.
  • Existing digital countermeasures — probing, authentication, and validation tools — will not transfer cleanly to ISC because analog fault signals can look like sensor noise and there are few intermediate checkpoints.
  • Health-monitoring ISC devices deployed in public places will need lightweight integrity checks that work without probing individual sensing elements.
  • The comparison predicts a security trade-off: deeper integration shrinks the remotely accessible attack surface but pushes attacks toward physical, customized, hard-to-detect forms.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the trend holds, the strongest countermeasures will use the sensing physics itself — for example, fingerprinting material response or treating the sensor's characteristic curve as a tamper-evident seal — since digital authentication has no natural anchor in a fused analog device.
  • A direct testable extension is to measure detection latency for a deliberately inserted counterfeit ferroelectric layer in a true device-level ISC versus an equivalent traditional chain; the paper's delayed-detection claim predicts a measurable lag.
  • The board-level demo implies a broader statement the authors do not make: any system that trusts an unauthenticated analog sensor-to-computation link, ISC or not, is open to low-cost environmental manipulation; ISC matters because it deliberately removes the digitization that would otherwise bound the attack.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. This paper surveys in-sensor computing (ISC) research, argues that ISC systems introduce new hardware security challenges at board, chip, and device levels, contrasts these with traditional sensor-involved computing (TSC), and presents two proof-of-concept demos: a counterfeit attack on a ferroelectric tunnel FET (FET) based gustatory system and an environmental interference attack on an optical sensor-based emotion recognition system. The paper claims to be the first work to analyze security challenges in ISC systems and to compare TSC and ISC security.

Significance. If the analysis is supported, the paper would make a useful contribution by systematically categorizing ISC attack surfaces and motivating countermeasure research. The structured literature review and the three-level attack taxonomy are valuable framing devices, and the paper identifies plausible threat vectors, such as analog side-channel leakage and counterfeit device-level attacks. However, the empirical substantiation is currently weak: Demo 2 does not actually implement in-sensor computation, and Demo 1 is only a conceptual simulation without quantitative results. The paper is best read as a position paper that outlines potential threats rather than a validated experimental study.

major comments (3)
  1. [Section IV.B and Fig. 8] Demo 2 does not implement an in-sensor computing system as defined in Section I. The setup uses a conventional CMOS sensor (OV7670) transmitting image data over a serial data bus to an external Py-Feat classifier, which is a traditional sensor-involved computing (TSC) configuration, not ISC. Since no computation occurs inside the sensor and no TSC baseline is provided, the experiment cannot establish that ISC systems are uniquely vulnerable to environmental interference at the board level, nor that the attack is new to ISC. This invalidates one of the two proof-of-concept demonstrations and weakens the central claim that the demos inspire countermeasures against unique ISC hardware security threats.
  2. [Section IV.A and Fig. 7] Demo 1 is described only qualitatively: the I-V characteristic change and the resulting detection output offset are depicted in Fig. 7(c) and (d) without any numerical data, simulation results, error bars, or repeatability metrics. The claim that a small change in FE-oxide thickness in a counterfeit device leads to a wrong biomolecule recognition is therefore unsupported. As this is the only demonstration of the device-level counterfeit attack, the empirical basis for that attack surface is not established.
  3. [Section III.A and Table I] The entries in Table I, such as 'ISC attacks require full knowledge of the entire system' and 'attack detection is complicated', are presented as established facts but are not derived from the demos or a systematic analysis. Some entries conflate limited accessibility with requiring full knowledge, and the threat models differ substantially across board-, chip-, and device-level ISC. The paper should present these comparisons explicitly as hypotheses or support them with concrete case studies and a defined attacker model.
minor comments (5)
  1. [Abstract and Section I] The claim 'to the best of our knowledge, this is the first work that analyzes security challenges in ISC systems' is stated twice without a systematic search of security literature in adjacent paradigms such as processing-in-memory, analog computing, or sensor security; please temper the claim to 'to our knowledge' and describe the search criteria.
  2. [Section IV.B and VI] The phrase 'proof-the-concept' appears twice and should be corrected to 'proof-of-concept'.
  3. [Figure 2] The y-axis of the 'historical progress' chart is not labeled; please clarify whether the chart plots cumulative publication counts or a different metric, and describe the search and selection methodology for the literature data in Fig. 3.
  4. [Reference [28]] Reference [28] is formatted as 'I. OmniVision Technologies'; the correct style is 'OmniVision Technologies' without the initial.
  5. [Section III.B.1] The sentence 'analog signals may reveal more details than the digital format since analog signals have frequency, magnitude, and phase' is unclear because digital signals also carry these properties; please specify which physical attributes of the analog sensor output are measurably more informative to an attacker.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: the attack-surface analysis is reasoned from the ISC architecture and the demos are illustrative, not fitted predictions.

full rationale

The paper does not derive any result from fitted parameters, nor does it rename empirical patterns as predictions. The attack scenarios at board, chip, and device level are reasoned from the defining features of in-sensor computing (e.g., analog or semi-analog signals, lack of probing points, and tight integration). The two demos are presented as proof-of-concept illustrations, not as statistical predictions: Demo 1 assumes a counterfeit material change and then shows its simulated effect on I-V and frequency, while Demo 2 shows that an environmental interference circuit can alter an external classifier's output. Neither demo's conclusion is forced by construction from a fit. The authors' self-citations ([2], [5], [6]) appear only as background on wearable sensors and prior sensor-security work; the central security analysis does not depend on those citations being true. One validity concern is that Demo 2 uses a conventional CMOS sensor with an external Py-Feat model, which is not an in-sensor computing configuration; however, that is an external-validity or correctness issue, not a circularity pattern, because the paper does not claim the demo's output is predicted from a fitted model or from a self-cited theorem. Overall, the derivation chain is self-contained and non-circular.

Assumptions & free parameters 0 free parameters · 3 assumptions · 0 invented entities

No free parameters, no invented physical entities. The analysis rests on the architectural premise of ISC and on transferring known hardware security categories to this new context.

assumptions (3)
  • domain assumption ISC systems integrate sensing, memory, and computation into one compact unit, with less ADC and data transmission.
    The paper's entire threat analysis depends on this architecture (Fig. 1, Sections II-B, III-A).
  • domain assumption The security categories used for traditional systems (fault attacks, side-channel, Trojan, counterfeit) apply to ISC.
    Section III-A extends TSC attacks to ISC without establishing that these categories are complete or that ISC introduces fundamentally new categories.
  • domain assumption The demos' physical setups (FE-oxide thickness change, photo-resistor bus interference) reflect plausible ISC implementation scenarios.
    Section IV assumes these modeled changes represent realistic attacks on ISC hardware.

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Cite this review

Pith. "Pith review of New Security Challenges Towards In-Sensor Computing Systems." pith.science (2026). https://pith.science/paper/KDFRY3MD

@misc{pith2026250205046,
  author       = {Pith},
  title        = {Pith review of: New Security Challenges Towards In-Sensor Computing Systems},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/KDFRY3MD}},
  note         = {Machine review of arXiv:2502.05046}
}
read the original abstract

Data collection and processing in advanced health monitoring systems are experiencing revolutionary change. In-Sensor Computing (ISC) systems emerge as a promising alternative to save energy on massive data transmission, analog-to-digital conversion, and ineffective processing. While the new paradigm shift of ISC systems gains increasing attention, the highly compacted systems could incur new challenges from a hardware security perspective. This work first conducts a literature review to highlight the research trend of this topic and then performs comprehensive analyses on the root of security challenges. This is the first work that compares the security challenges of traditional sensor-involved computing systems and emerging ISC systems. Furthermore, new attack scenarios are predicted for board-, chip-, and device-level ISC systems. Two proof-of-concept demos are provided to inspire new countermeasure designs against unique hardware security threats in ISC systems.

Figures

Figures reproduced from arXiv: 2502.05046 by the authors.

Figure 1
Figure 1. A conceptual diagram for in-sensor computing. (a) Overview and [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 3
Figure 3. In-sensor computing publications from 2020 to 2024 (Sept.) (a) [PITH_FULL_IMAGE:figures/full_fig_p002_3.png] view at source ↗
Figure 4
Figure 4. A bar chart for primary focuses of the existing publications. [PITH_FULL_IMAGE:figures/full_fig_p002_4.png] view at source ↗
Figures from the paper (4 more)
Figure 5
Figure 5. Figure 5: Attacks in different phases of ISC system’s design and deployment. [PITH_FULL_IMAGE:figures/full_fig_p003_5.png]
Figure 6
Figure 6. Figure 6: Attack surfaces at (a) board-level (b) chip-level (c) the device-level [PITH_FULL_IMAGE:figures/full_fig_p003_6.png]
Figure 8
Figure 8. Figure 8: Demo 2: Environmental interference attack on an optical-sensor [PITH_FULL_IMAGE:figures/full_fig_p004_8.png]
Figure 7
Figure 7. Figure 7: Demo 1: counterfeit attack on an ISC for biomolecule detection. [PITH_FULL_IMAGE:figures/full_fig_p004_7.png]

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Reference graph

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