Pith. sign in

REVIEW 4 major objections 5 minor 36 references

Characterization and Mitigation of ADC Noise by Reference Tuning in RRAM-Based Compute-In-Memory

T0 review · 4 major / 5 minor · reviewed 2026-08-08 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗ Review JSON

Pith's one-line read Per-module and per-ADC reference tuning recovers most accuracy lost to RRAM and ADC noise in compute-in-memory accelerators.

desk verdict The characterization data is real, but the paper's own drone results contradict its central claim that reference tuning maintains robustness, so the mitigation story does not hold. read the letter →

arxiv 2502.05948 v1 pith:LKNNG5FY submitted 2025-02-09 cs.ET

Ying-Hao Wei , Zishen Wan , Brian Crafton , Samuel Spetalnick , Arijit Raychowdhury This is my paper · ORCID
classification cs.ET
keywords compute-in-memoryRRAMADCnoisereferencetuningreaddisturbeffectivebitsreinforcementlearninginjection
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper argues that a large share of the accuracy lost to analog noise in RRAM-based compute-in-memory (CIM) accelerators can be recovered by tuning the reference voltages of the output ADCs, without changing the network or retraining. Using measurements from a 40nm RRAM test chip, the authors build an 'effective bits' model that folds RRAM cell variability and ADC non-ideality into per-cell mean and variance statistics, then inject those statistics as noise into simulations of four workloads: VGG-8 on CIFAR-10, ResNeXt-50 on ImageNet, a GridWorld agent, and a drone-navigation reinforcement-learning agent. They report that per-module reference tuning keeps VGG-8 within about 2.3 points of its clean quantized baseline, while the ImageNet model needs finer per-ADC tuning to stay near its baseline. The paper also characterizes read disturb and shows that a low-voltage read mode limits resistance drift. If the model is representative, the practical consequence is that a simple hardware calibration knob can substitute for more expensive retraining or redundancy in many CIM deployments.

What carries the argument

The 'effective bits' model: each RRAM cell's 0/1 contribution is replaced by a normal random variable whose mean and standard deviation are extracted from test-chip measurements, separately for HRS(0) and LRS(1), within 9-cell accumulation groups. A least-absolute-deviation fit over 256 random input vectors assigns an effective bit value and a residual error distribution to every cell; the residual is injected as dynamic noise. ADC reference tuning adjusts offset, step size, and bitline target voltage at global, per-module, or per-ADC granularity, which shifts the effective-bit distributions and therefore the end-task accuracy.

What would settle it

Run the same four workloads on the actual test chip with the same per-module/per-ADC reference settings and compare end-task accuracy to the simulated numbers, e.g., VGG-8 should land near 87.7% on CIFAR-10; a systematic gap would show the independent-Gaussian effective-bit model is not capturing real noise.

Watch

Extended reading notes

Core claim

The paper's claim is that an RRAM CIM macro's end-to-end inference error can be decomposed into a static component (per-cell effective 0/1 bits, measured by fitting 256 random 9-bit vectors per accumulation group with least absolute deviation) and a dynamic residual, and that both components shift with the ADC reference settings. When the ADC references are tuned per module (8 ADCs) or per ADC, the simulated accuracy of supervised classifiers and RL agents recovers most of the gap to their quantization-only baselines; per-ADC tuning is required for the high-precision ImageNet/ResNeXt case. The read-disturb experiments show HRS cells drift toward LRS under stress, which can push CIFAR-10 accuracy from 87% to 66%, and the paper's low-voltage read mode keeps the shifts minimal. In short, the central discovery is that reference tuning is a viable, low-cost mitigation knob for CIM noise.

Load-bearing premise

The measured per-cell effective-bit distributions from 10 modules (80 ADCs) on this one 40nm chip are treated as the noise experienced by the simulated networks, with independent Gaussian sampling per bit; if those measurements don't represent real deployment noise, the reported tuning benefits wouldn't transfer.

Editorial extensions

If this is right

  • Per-module reference tuning recovers most of the noise-induced accuracy drop on CIFAR-10/VGG-8, with simulated accuracy at 87.7% versus a 90.03% clean baseline.
  • The ImageNet/ResNeXt-50 workload fails with per-module tuning and requires per-ADC tuning, landing at 82% versus an 83% baseline, so finer-grained tuning is the fallback when module-level settings are insufficient.
  • In GridWorld, the per-module-tuned noise-injected policy still wins 78.2% of missions compared with a 95.5% win rate for the quantized-only policy, showing time-dependent RL tasks are more sensitive to CIM noise.
  • Read-disturb stress can drop CIFAR-10 accuracy from 87% to 66%, and operating at lower read voltages keeps resistance shifts small, so low-voltage read is a mitigation for long-horizon deployments.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the effective-bit statistics generalize from this test chip to other RRAM macros, reference tuning could be applied as a per-instance calibration step after fabrication, reducing the need for noise-aware retraining on every chip.
  • The per-ADC versus per-module distinction suggests a build-time knob: designers can choose ADC reference granularity based on the precision demands of the target workload, with per-ADC only needed for high-precision tasks.
  • The read-disturb measurements imply a testable design rule: keeping bitline read voltage near 100-300mV should preserve the tuned effective-bit distributions over long inference runs; measuring drift after many read cycles would validate the claimed stability.
  • The same noise-injection pipeline could be used to rank other mitigation levers, such as write-verify or ECC, against reference tuning on the same four workloads, giving hardware designers a common benchmark.
Share X Bluesky LinkedIn Reddit HN

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. The paper presents a measurement-based noise model for RRAM compute-in-memory (CIM) systems, using a 40nm test chip to extract effective-bit statistics and read-disturb shifts. It then simulates the impact of this noise on four workloads: VGG-8/CIFAR-10, ResNeXt50/ImageNet, a GridWorld MLP, and drone autonomous navigation. The central claim is that per-module or per-ADC reference tuning effectively mitigates CIM noise impacts across time-independent and time-dependent tasks. The paper reports accuracy degradations for supervised tasks and task-success metrics for reinforcement learning tasks, and concludes that per-module/per-ADC tuning maintains system robustness.

Significance. The work provides valuable hardware characterization data from a 40nm RRAM test chip, including per-cell effective-bit distributions and read-disturb trends, and it connects these measurements to application-level simulation. If the noise model were validated and the tuning results were consistently positive, the paper would offer a practical calibration strategy for RRAM CIM accelerators. However, the central claim is directly contradicted by the paper's own drone-navigation results, and the simulation methodology lacks hardware-in-the-loop validation on the evaluated workloads. The paper's contribution is therefore currently more of a measurement methodology and cautionary negative result than a demonstrated mitigation technique.

major comments (4)
  1. [§V-B, Table III] Table III directly contradicts the paper's conclusion that per-module/per-ADC tuning 'is effective in maintaining system robustness.' For drone autonomous navigation, the quantize-only baseline achieves an MSF of 899.38m, while per-module tuning yields MSF <20m and per-ADC tuning yields 690.99m. Since higher MSF is better, both tuning configurations degrade performance relative to simply quantizing without noise injection, and per-module tuning is catastrophic. The text accompanying Table III states the opposite of the data. This is a load-bearing inconsistency: the central claim of the abstract and conclusion is falsified by the paper's own experimental evidence.
  2. [§III-C, §IV-B] The noise injection model is built by fitting effective-bit means and standard deviations from 10 test-chip modules (80 ADCs) and then sampling independent Gaussian noise in simulation. The manuscript provides no validation that this fitted noise model reproduces the actual accuracy or task-success degradation for any of the four evaluated workloads. In particular, there is no hardware-in-the-loop measurement on CIFAR-10, ImageNet, GridWorld, or the drone task. Without such validation, the simulated accuracy drops are a propagation of the fitted noise parameters rather than an independent prediction, and the claimed tuning benefits may not transfer to real deployments. The read-disturb analysis is also based on a single module and an accelerated stress condition, leaving the representativeness of that module and condition unaddressed.
  3. [§V-A, Table I(b)] The ImageNet results are presented as 'Imagenet-1k / ResNeXT50-32x4d' in the text, but Table I(b) reports a baseline of 83% on a 'reduced-set' and a noise-injected accuracy of 82% on the same reduced set. The abstract and introduction imply full ImageNet-1K evaluation. The manuscript never specifies the size or composition of the reduced subset, nor does it justify that the subset is representative of full ImageNet. This is important because the paper's conclusion about complex supervised workloads rests entirely on this single reduced-set result, and per-module tuning is acknowledged to fail outright for this network, requiring per-ADC tuning instead. The claim that 'per-module/per-ADC tuning is effective' is therefore not supported for this workload without additional details.
  4. [Tables I–III] No error bars, confidence intervals, or number of random seeds are reported for any accuracy, win-rate, or MSF measurement. In particular, Table III reports MSF <20m for per-module tuning as a point value without indicating how many drone episodes were evaluated or how much variance exists across episodes. Given the catastrophic drop from 899m to <20m, it is possible that a single unlucky rollout dominates this result. The absence of statistical characterization makes it impossible to assess whether the reported differences, including the claimed benefits of per-ADC tuning on ImageNet and GridWorld, are significant. This is a methodological gap that affects every quantitative conclusion in Section V.
minor comments (5)
  1. [Fig. 1 caption] The caption describes reinforcement learning as 'unsupervised learning'; reinforcement learning is neither supervised nor unsupervised in the standard taxonomy, and the phrase is misleading.
  2. [§III-A] The description of the absolute binning approach and the example in Fig. 3 are difficult to follow; the text should define 'golden value' explicitly and clarify how the dominant-representation rule is applied across the full 16-state ADC output.
  3. [§III-B] The fitting procedure is said to minimize the sum of absolute differences, but the number of fitted parameters per cell and the degrees of freedom of the residual error are not stated. Adding this detail would make the extracted effective-bit statistics more reproducible.
  4. [§IV-A] Fig. 7 reports resistance shift under different BL voltages, but the text does not state the number of cells averaged or the measurement conditions (e.g., temperature and cycle count) for each curve. This makes the claim of 'minimal resistance shift' hard to assess.
  5. [References] Reference [17] is cited for Neurosim, but the modified version with layer scaling and WAGE quantization is not publicly identifiable; the authors should state which version or commit of Neurosim was used and whether the modifications are available.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: hardware-calibrated noise model is applied to unseen workloads; tuning comparison is measured, not fitted to target accuracies.

full rationale

The paper's derivation chain is not circular. The central model quantities (effective bits, their means/standard deviations, and residual error) are fitted in Sec. III-B to microbenchmark measurements (256 random 9-bit vectors per accumulation group on a 40nm RRAM test chip), not to the four workload accuracies or to the tuning comparisons. Sec. III-C injects these fitted distributions into a NeuroSim-based simulator and reports accuracies for VGG-8/CIFAR-10, ResNeXt-50/ImageNet, GridWorld, and drone navigation. Because the fitted parameters are external hardware measurements and the target outputs (accuracy, win rate, MSF) are not used in the fit, the simulation is a propagation of measured device behavior, not a tautology. The per-module versus per-ADC tuning comparison is generated by applying different reference configurations on the chip, measuring the resulting effective-bit distributions, and simulating; the comparison is not a parameter fitted to reproduce the conclusion. No uniqueness theorem or load-bearing self-citation is invoked; references [20]-[23] are prior hardware prototypes used as measurement vehicles, which is legitimate experimental evidence. The manuscript does contain a notable internal inconsistency -- Table III shows per-module tuning MSF < 20m and per-ADC tuning MSF 690.99m, both worse than the quantize-only 899.38m, while Sec. V-B claims tuning 'is effective in maintaining system robustness' -- but that is a correctness/consistency flaw, not circularity. Similarly, the single-chip 80-ADC noise sample and the Gaussian independence assumption are external-validity concerns, not circularity. No specific equation or claim reduces by construction to its own inputs.

Assumptions & free parameters 5 free parameters · 5 assumptions · 0 invented entities

The simulation results are derived from fitted effective-bit distributions and the listed assumptions. The central quantitative outputs, the accuracy and MSF values, are consequences of these fitted inputs plus the simulator, so the ledger names the measured or assumed quantities the paper pulls from the test chip and the domain.

free parameters (5)
  • HRS effective bit mean = not given in text
    Mean of the fitted effective-bit distribution for HRS cells, obtained by minimizing the sum of absolute differences between golden and actual outputs in Sec. III-B.
  • LRS effective bit mean = not given in text
    Mean of the fitted effective-bit distribution for LRS cells, measured on the test chip and used as the noise injection value in Sec. III-C.
  • HRS/LRS effective bit standard deviations = not given in text
    Standard deviations of the effective-bit distributions for both states, used to generate random normal distributions for noise injection in Sec. III-C.
  • Residual dynamic error distribution = not given in text
    Auxiliary error from the least-absolute-deviation fitting procedure, aggregated as a dynamic noise source in Sec. III-B.
  • Read-disturb effective bit shift = not given in text
    Shift in effective bit means after accelerated stress (1300mV BL, 10 cycles of 50k stresses), used to estimate CIFAR-10 accuracy drop in Sec. IV-B.
assumptions (5)
  • domain assumption Effective bits are Gaussian and independently distributed across cells
    Sec. III-C replaces original bits with samples from normal distributions formed from measured means and standard deviations; no evidence of Gaussianity or independence is provided.
  • ad hoc to paper The least-absolute-difference fit yields the true effective bits
    Sec. III-B chooses this fitting criterion without justification, and the residual error is absorbed as dynamic noise rather than validated.
  • domain assumption Accelerated read-disturb stress extrapolates to low-voltage operation
    Sec. IV uses 1300mV BL stress to observe shifts, then concludes that low-voltage read (100-300mV) avoids them; no validated model of shift versus voltage and time is given.
  • ad hoc to paper The reduced ImageNet subset is representative of full ImageNet
    Table I(b) reports accuracy on a 'reduced-set' without specifying the subset size or composition, so the transferability of the reported 82% to full ImageNet is unknown.
  • domain assumption Neurosim faithfully reproduces hardware noise effects on the evaluated workloads
    The noise injection is performed in a modified Neurosim with no hardware-in-the-loop validation on CIFAR-10, ImageNet, GridWorld, or the drone task.

how reviews work

0 comments
Cite this review

Pith. "Pith review of Characterization and Mitigation of ADC Noise by Reference Tuning in RRAM-Based Compute-In-Memory." pith.science (2026). https://pith.science/paper/LKNNG5FY

@misc{pith2026250205948,
  author       = {Pith},
  title        = {Pith review of: Characterization and Mitigation of ADC Noise by Reference Tuning in RRAM-Based Compute-In-Memory},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/LKNNG5FY}},
  note         = {Machine review of arXiv:2502.05948}
}
read the original abstract

With the escalating demand for power-efficient neural network architectures, non-volatile compute-in-memory designs have garnered significant attention. However, owing to the nature of analog computation, susceptibility to noise remains a critical concern. This study confronts this challenge by introducing a detailed model that incorporates noise factors arising from both ADCs and RRAM devices. The experimental data is derived from a 40nm foundry RRAM test-chip, wherein different reference voltage configurations are applied, each tailored to its respective module. The mean and standard deviation values of HRS and LRS cells are derived through a randomized vector, forming the foundation for noise simulation within our analytical framework. Additionally, the study examines the read-disturb effects, shedding light on the potential for accuracy deterioration in neural networks due to extended exposure to high-voltage stress. This phenomenon is mitigated through the proposed low-voltage read mode. Leveraging our derived comprehensive fault model from the RRAM test-chip, we evaluate CIM noise impact on both supervised learning (time-independent) and reinforcement learning (time-dependent) tasks, and demonstrate the effectiveness of reference tuning to mitigate noise impacts.

Figures

Figures reproduced from arXiv: 2502.05948 by the authors.

Figure 1
Figure 1. Impact of noises on different scenarios, including super￾vised learning (time-independent) and unsupervised learning (time￾dependent). While some adapted effectively to per-module reference adjustments, others necessitated a more refined per-ADC tuning. necessitates an intricate simulation. Hence, our goal is to create a streamlined model that encompasses primary noise sources. This model aims to gauge the feasibili… view at source ↗
Figure 3
Figure 3. Mapping voltage states to actual value, where x-axis is golden value and y-axis is voltage states. Red boxes indicate that the voltage state is assigned to that specific target code. We define a sequence of nine consecutive cells within a column as an “acc-9 group.” Following this definition, we apply 256 randomly generated 9-bit vectors to every “acc-9 group” within a matrix of 81 rows and 64 columns, covering the … view at source ↗
Figure 4
Figure 4. The histogram of the correct output, under a CIM array (9 × 64 accumulate groups, spams across 8 ADCs) of 50% HRS and 50% LRS. The input consists of 256 different combinations among 9 WLs [PITH_FULL_IMAGE:figures/full_fig_p003_4.png] view at source ↗
Figures from the paper (4 more)
Figure 5
Figure 5. Figure 5: Measuring the effective bits of (a) actual v.s. golden response and (b) actual v.s. fitted response, under 512 WL combinations. for each cell within an accumulation group. We’ll reference this element as the static error component. It’s crucial to emphasize that the fi…
Figure 6
Figure 6. Figure 6: The effective bit (top) and error (bottom) across the module, contains results from all 8 ADCs. The error is calculated by accumu￾lating the difference between golden and fitted output of 256 samples [PITH_FULL_IMAGE:figures/full_fig_p003_6.png]
Figure 8
Figure 8. Figure 8: (a) Effective bit map for pre-shift, (b) Effective bit map for post-shift [PITH_FULL_IMAGE:figures/full_fig_p004_8.png]
Figure 9
Figure 9. Figure 9: Effective bit mean of HRS(0) (orange)/LRS(1) (blue) and accuracy of CIFAR-10 (red) v.s. cycle. Following the determination of effective bit shifts, we incor￾porate the resistance shifts into VGG-8, based on the parame￾ters measured from module. We observe that the shif…

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

36 extracted references · 35 canonical work pages

  1. [1]

    Low power and high speed bipolar switching with a thin reactive ti buffer layer in robust hfo2 based rram,

    H. Y . Lee, P. S. Chen, T. Y . Wu, Y . S. Chen, C. C. Wang, P. J. Tzeng, C. H. Lin, F. Chen, C. H. Lien, and M.-J. Tsai, “Low power and high speed bipolar switching with a thin reactive ti buffer layer in robust hfo2 based rram,” in 2008 IEEE International Electron Devices Meeting , pp. 1–4, 2008

    work page 2008

  2. [2]

    Adapting magnetoresistive memory devices for accurate and on-chip-training-free in-memory computing,

    Z. Xiao, V . B. Naik, J. H. Lim, Y . Hou, Z. Wang, and Q. Shao, “Adapting magnetoresistive memory devices for accurate and on-chip-training-free in-memory computing,” Science Advances, vol. 10, no. 38, 2024

    work page 2024

  3. [3]

    Pcm-based analog compute-in-memory: Impact of device non-idealities on inference accuracy,

    X. Sun, W. S. Khwa, Y . S. Chen, C. H. Lee, H. Y . Lee, S. M. Yu, R. Naous, J. Y . Wu, T. C. Chen, X. Bao, M. F. Chang, C. H. Diaz, H.- S. P. Wong, and K. Akarvardar, “Pcm-based analog compute-in-memory: Impact of device non-idealities on inference accuracy,”IEEE Transactions on Electron Devices , vol. 68, no. 11, pp. 5585–5591, 2021

    work page 2021

  4. [4]

    See-mcam: Scalable multi-bit fefet content addressable memories for energy efficient associative search,

    S. Shou, C.-K. Liu, S. Yun, Z. Wan, K. Ni, M. Imani, X. S. Hu, J. Yang, C. Zhuo, and X. Yin, “See-mcam: Scalable multi-bit fefet content addressable memories for energy efficient associative search,” in 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp. 1–9, IEEE, 2023

    work page 2023

  5. [5]

    Finding a roadmap to achieve large neuromorphic hardware systems,

    J. Hasler and H. Marr, “Finding a roadmap to achieve large neuromorphic hardware systems,” Frontiers in Neuroscience, vol. 7, 2013

    work page 2013

  6. [6]

    Compute-in-memory chips for deep learning: Recent trends and prospects,

    S. Yu, H. Jiang, S. Huang, X. Peng, and A. Lu, “Compute-in-memory chips for deep learning: Recent trends and prospects,” IEEE Circuits and Systems Magazine, vol. 21, no. 3, pp. 31–56, 2021

    work page 2021

  7. [7]

    Challenges and trends of sram-based computing-in-memory for ai edge devices,

    C.-J. Jhang, C.-X. Xue, J.-M. Hung, F.-C. Chang, and M.-F. Chang, “Challenges and trends of sram-based computing-in-memory for ai edge devices,” IEEE Transactions on Circuits and Systems I: Regular Papers , vol. 68, no. 5, pp. 1773–1786, 2021

    work page 2021

  8. [8]

    Dnn+ neurosim: An end- to-end benchmarking framework for compute-in-memory accelerators with versatile device technologies,

    X. Peng, S. Huang, Y . Luo, X. Sun, and S. Yu, “Dnn+ neurosim: An end- to-end benchmarking framework for compute-in-memory accelerators with versatile device technologies,” in 2019 IEEE international electron devices meeting (IEDM) , pp. 32–5, IEEE, 2019

    work page 2019

Show all 36 references
  1. [9]

    A 73.53 tops/w 14.74 tops heterogeneous rram in-memory and sram near-memory soc for hybrid frame and event-based target tracking,

    M. Chang, A. S. Lele, S. D. Spetalnick, B. Crafton, S. Konno, Z. Wan, A. Bhat, W.-S. Khwa, Y .-D. Chih, M.-F. Chang, et al., “A 73.53 tops/w 14.74 tops heterogeneous rram in-memory and sram near-memory soc for hybrid frame and event-based target tracking,” in2023 IEEE Internat...

    2023

  2. [10]

    A heterogeneous rram in-memory and sram near-memory soc for fused frame and event- based target identification and tracking,

    A. S. Lele, M. Chang, S. D. Spetalnick, B. Crafton, S. Konno, Z. Wan, A. Bhat, W.-S. Khwa, Y .-D. Chih, M.-F. Chang, et al., “A heterogeneous rram in-memory and sram near-memory soc for fused frame and event- based target identification and tracking,” IEEE Journal of Solid-Sta...

    2023

  3. [11]

    Computation-oriented fault-tolerance schemes for rram computing systems,

    W. Huangfu, L. Xia, M. Cheng, X. Yin, T. Tang, B. Li, K. Chakrabarty, Y . Xie, Y . Wang, and H. Yang, “Computation-oriented fault-tolerance schemes for rram computing systems,” in 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC) , pp. 794–799, 2017

    2017

  4. [12]

    Rram-ecc: Improving reliability of rram-based compute in-memory,

    Z. Wan, B. Crafton, S. Spetalnick, J.-H. Yoon, and A. Raychowdhury, “Rram-ecc: Improving reliability of rram-based compute in-memory,” in 13th Annual Non-Volatile Memories Workshop (NVMW) , 2022

    2022

  5. [13]

    Improving compute in-memory ecc relia- bility with successive correction,

    B. Crafton, Z. Wan, S. Spetalnick, J.-H. Yoon, W. Wu, C. Tokunaga, V . De, and A. Raychowdhury, “Improving compute in-memory ecc relia- bility with successive correction,” in Proceedings of the 59th ACM/IEEE Design Automation Conference , pp. 745–750, 2022

    2022

  6. [14]

    Fault-tolerant training with on-line fault detection for rram-based neural computing systems,

    L. Xia, M. Liu, X. Ning, K. Chakrabarty, and Y . Wang, “Fault-tolerant training with on-line fault detection for rram-based neural computing systems,” in 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 1–6, 2017

    2017

  7. [15]

    Automated quantization range mapping for dac/adc non-linearity in computing-in- memory,

    C.-T. Huang, Y .-C. Chuang, M.-G. Lin, and A.-Y . A. Wu, “Automated quantization range mapping for dac/adc non-linearity in computing-in- memory,” in2022 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2998–3002, IEEE, 2022

    2022

  8. [16]

    Compute in-memory with non-volatile elements for neural networks: A review from a co-design perspective,

    W. Haensch, A. Raghunathan, K. Roy, B. Chakrabarti, C. M. Phatak, C. Wang, and S. Guha, “Compute in-memory with non-volatile elements for neural networks: A review from a co-design perspective,” Advanced Materials, vol. 35, no. 37, p. 2204944, 2023

    2023

  9. [17]

    Dnn+neurosim v2.0: An end-to-end benchmarking framework for compute-in-memory accelerators for on-chip training,

    X. Peng, S. Huang, H. Jiang, A. Lu, and S. Yu, “Dnn+neurosim v2.0: An end-to-end benchmarking framework for compute-in-memory accelerators for on-chip training,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 11, pp. 2306–2319, 2021

    2021

  10. [18]

    Design of reliable dnn accel- erator with un-reliable reram,

    Y . Long, X. She, and S. Mukhopadhyay, “Design of reliable dnn accel- erator with un-reliable reram,” in 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE) , pp. 1769–1774, 2019

    2019

  11. [19]

    Berry: Bit error robustness for energy- efficient reinforcement learning-based autonomous systems,

    Z. Wan, N. Chandramoorthy, K. Swaminathan, P.-Y . Chen, V . J. Reddi, and A. Raychowdhury, “Berry: Bit error robustness for energy- efficient reinforcement learning-based autonomous systems,” in2023 60th ACM/IEEE Design Automation Conference (DAC) , pp. 1–6, IEEE, 2023

    2023

  12. [20]

    A 40nm 64kb 26.56 tops/w 2.37 mb/mm 2 rram binary/compute-in-memory macro with 4.23x improvement in density and >75% use of sensing dynamic range,

    S. D. Spetalnick, M. Chang, B. Crafton, W.-S. Khwa, Y .-D. Chih, M.-F. Chang, and A. Raychowdhury, “A 40nm 64kb 26.56 tops/w 2.37 mb/mm 2 rram binary/compute-in-memory macro with 4.23x improvement in density and >75% use of sensing dynamic range,” in 2022 IEEE International So...

    2022

  13. [21]

    A 40-nm, 64-kb, 56.67 tops/w voltage-sensing computing-in-memory/digital rram macro supporting iterative write with verification and online read-disturb detection,

    J.-H. Yoon, M. Chang, W.-S. Khwa, Y .-D. Chih, M.-F. Chang, and A. Raychowdhury, “A 40-nm, 64-kb, 56.67 tops/w voltage-sensing computing-in-memory/digital rram macro supporting iterative write with verification and online read-disturb detection,” IEEE Journal of Solid- State C...

    2022

  14. [22]

    Characterization and mitigation of ir-drop in rram-based compute in- memory,

    B. Crafton, C. Talley, S. Spetalnick, J.-H. Yoon, and A. Raychowdhury, “Characterization and mitigation of ir-drop in rram-based compute in- memory,” in2022 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 70–74, 2022

    2022

  15. [23]

    29.1 a 40nm 64kb 56.67 tops/w read-disturb-tolerant compute-in-memory/digital rram macro with active-feedback-based read and in-situ write verification,

    J.-H. Yoon, M. Chang, W.-S. Khwa, Y .-D. Chih, M.-F. Chang, and A. Raychowdhury, “29.1 a 40nm 64kb 56.67 tops/w read-disturb-tolerant compute-in-memory/digital rram macro with active-feedback-based read and in-situ write verification,” in 2021 IEEE International Solid-State Ci...

    2021

  16. [24]

    A compute-in-memory chip based on resistive random-access memory,

    W. Wan, R. Kubendran, C. Schaefer, S. B. Eryilmaz, W. Zhang, D. Wu, S. Deiss, P. Raina, H. Qian, B. Gao, et al., “A compute-in-memory chip based on resistive random-access memory,” Nature, vol. 608, no. 7923, pp. 504–512, 2022

    2022

  17. [25]

    Compute-in-memory with emerging nonvolatile-memories: Challenges and prospects,

    S. Yu, X. Sun, X. Peng, and S. Huang, “Compute-in-memory with emerging nonvolatile-memories: Challenges and prospects,” in 2020 ieee custom integrated circuits conference (cicc) , pp. 1–4, IEEE, 2020

    2020

  18. [26]

    Rram for compute-in-memory: From inference to training,

    S. Yu, W. Shim, X. Peng, and Y . Luo, “Rram for compute-in-memory: From inference to training,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 7, pp. 2753–2765, 2021

    2021

  19. [27]

    A 40nm rram compute-in- memory macro featuring on-chip write-verify and offset-cancelling adc references,

    W. Li, X. Sun, H. Jiang, S. Huang, and S. Yu, “A 40nm rram compute-in- memory macro featuring on-chip write-verify and offset-cancelling adc references,” in ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), pp. 79–82, 2021

    2021

  20. [28]

    Impact of read disturb on multi- level rram based inference engine: Experiments and model prediction,

    W. Shim, Y . Luo, J.-s. Seo, and S. Yu, “Impact of read disturb on multi- level rram based inference engine: Experiments and model prediction,” in 2020 IEEE International Reliability Physics Symposium (IRPS) , pp. 1–5, 2020

    2020

  21. [29]

    Aggregated resid- ual transformations for deep neural networks,

    S. Xie, R. Girshick, P. Doll ´ar, Z. Tu, and K. He, “Aggregated resid- ual transformations for deep neural networks,” in Proceedings of the IEEE conference on computer vision and pattern recognition (CVPR) , pp. 1492–1500, 2017

    2017

  22. [30]

    Training and inference with integers in deep neural networks,

    S. Wu, G. Li, F. Chen, and L. Shi, “Training and inference with integers in deep neural networks,” arXiv preprint arXiv:1802.04680 , 2018

    2018 arXiv

  23. [31]

    Quarl: Quantization for fast and environmentally sustainable reinforcement learning,

    S. Krishnan, M. Lam, S. Chitlangia, Z. Wan, G. Barth-Maron, A. Faust, and V . J. Reddi, “Quarl: Quantization for fast and environmentally sustainable reinforcement learning,” arXiv preprint arXiv:1910.01055 , 2019

    1910 arXiv

  24. [32]

    Analyzing and improving fault tolerance of learning-based navigation systems,

    Z. Wan, A. Anwar, Y .-S. Hsiao, T. Jia, V . J. Reddi, and A. Raychowdhury, “Analyzing and improving fault tolerance of learning-based navigation systems,” in 2021 58th ACM/IEEE Design Automation Conference (DAC), pp. 841–846, IEEE, 2021

    2021

  25. [33]

    Frl-fi: Transient fault analysis for federated reinforce- ment learning-based navigation systems,

    Z. Wan, A. Anwar, A. Mahmoud, T. Jia, Y .-S. Hsiao, V . J. Reddi, and A. Raychowdhury, “Frl-fi: Transient fault analysis for federated reinforce- ment learning-based navigation systems,” in 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) , pp. 430–435, ...

    2022

  26. [34]

    Autonomous navigation via deep reinforcement learning for resource constraint edge nodes using transfer learning,

    A. Anwar and A. Raychowdhury, “Autonomous navigation via deep reinforcement learning for resource constraint edge nodes using transfer learning,” IEEE Access, vol. 8, pp. 26549–26560, 2020

    2020

  27. [35]

    Analyzing and improving resilience and robustness of au- tonomous systems,

    Z. Wan, K. Swaminathan, P.-Y . Chen, N. Chandramoorthy, and A. Ray- chowdhury, “Analyzing and improving resilience and robustness of au- tonomous systems,” in Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design , pp. 1–9, 2022

    2022

  28. [36]

    Mavfi: An end-to-end fault analysis framework with anomaly detection and recovery for micro aerial vehicles,

    Y .-S. Hsiao, Z. Wan, T. Jia, R. Ghosal, A. Mahmoud, A. Raychowdhury, D. Brooks, G.-Y . Wei, and V . J. Reddi, “Mavfi: An end-to-end fault analysis framework with anomaly detection and recovery for micro aerial vehicles,” in 2023 Design, Automation & Test in Europe Conference ...

    2023

Pith tools

Reviewed August 8, 2026 · model on record in the stance chip above.