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REVIEW 3 major objections 5 minor 42 references

Data-aware Dynamic Execution of Irregular Workloads on Heterogeneous Systems

T0 review · 3 major / 5 minor · reviewed 2026-08-08 · deepseek-v4-flash

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Pith's one-line read A data-aware scheduler finds the optimal FPGA-GPU allocation in 77 of 86 workloads.

desk verdict A real FPGA-GPU scheduling testbed with a plausible dynamic scheduler, but the optimality claim is not supported by the DP algorithm as written and the headline numbers don't match the body. read the letter →

arxiv 2502.06304 v1 pith:6RXVXHRJ submitted 2025-02-10 cs.DC cs.AR

Zhenyu Bai , Dan Wu , Pranav Dangi , Dhananjaya Wijerathne , Venkata Pavan Kumar Miriyala , Tulika Mitra This is my paper · ORCID
classification cs.DCcs.AR
keywords dynamicschedulingheterogeneoussystemsFPGAGPUGNNinferencesliding-windowtransformerssparsity-awarepipelineparallelism
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper tries to establish that a scheduler which watches the input data can replace manual partitioning on heterogeneous GPU-FPGA systems. Its claim is that static, hand-tuned schedules are optimal only rarely, while the DyPE scheduler—using lightweight kernel performance models and a dynamic-programming search over pipeline stages—finds the optimal device allocation in 77 of 86 evaluated cases and loses only 3.95% on average when it misses. The payoff would matter because irregular workloads like GNN inference and sliding-window transformers change their sparsity and arithmetic intensity at runtime, so no fixed device assignment stays optimal. The paper backs the claim with measurements on a real testbed with direct GPU-to-FPGA data transfers, reporting 1.53x average throughput and 1.09x energy efficiency gains over a static baseline.

What carries the argument

The load-bearing object is the dynamic-programming table $dp[i][f][g]$ (with separate throughput and energy copies), which records the best pipeline for the first $i$ kernels using $f$ FPGAs and $g$ GPUs. The search groups several consecutive kernels into one pipeline stage, looks back at previous table entries for the remaining devices, and evaluates candidate stages through three functions: kernel performance estimation $f_{\mathrm{perf}}$, communication cost estimation $f_{\mathrm{comm}}$, and energy estimation $f_{\mathrm{eng}}$. The performance estimators are built by benchmarking kernels on synthetic input profiles and fitting linear regressions, with FPGA kernels using architecture-derived formulas that add a scaling factor fitted to the measured data. This machinery is what lets the scheduler compare many device allocations cheaply at runtime and re-run when input characteristics change.

What would settle it

Take a set of GNN or transformer inputs whose sparsity and arithmetic intensity fall outside the synthetic training range, run DyPE's chosen schedule on the hardware alongside an exhaustive enumeration of all pipeline-stage and device-count allocations, and compare ranking; if the enumerated optimum beats DyPE's choice by more than the reported few percent in a substantial share of cases, the transferability assumption fails.

Watch

Extended reading notes

Core claim

DyPE's central claim is that dynamic, input-aware scheduling is both necessary and sufficient for heterogeneous systems built from GPUs and FPGAs. It argues that the best device for a given kernel depends on data-dependent features such as sparsity and arithmetic intensity, which shift at runtime, so a schedule fixed at design time cannot track the optimum. The scheduler therefore takes a workload description, system specifications, kernel performance models, and user objectives, then builds a dynamic-programming table that groups consecutive kernels into pipeline stages and assigns each stage a number of FPGAs or GPUs, separately optimizing throughput and energy and reading out Pareto-optimal configurations—points where no alternative is better in both throughput and energy—through a balanced mode. On the authors' FPGA-GPU testbed, DyPE reports finding the optimal schedule in 77 of 86 cases, with an average 3.95% throughput or energy-efficiency loss in sub-optimal cases, and average gains of 1.53x throughput and 1.09x energy efficiency over a manually tuned static schedule and 1.44x and 1.66x over GPU-only execution.

Load-bearing premise

The results depend on the kernel performance models: linear regressions fit to synthetic profiles must predict real GNN and transformer runtimes well enough that the scheduler's ranking of device allocations is not inverted.

Editorial extensions

If this is right

  • A manually tuned static schedule is optimal in only 13 of the 86 evaluated cases, so any production heterogeneous system facing variable data should treat static allocation as a rarely optimal default.
  • DyPE recovers most of the gap by dynamic rescheduling: it finds the optimal schedule in 77 of 86 cases and keeps the average loss to 3.95% when it misses.
  • Over baselines, DyPE reports average 1.53x throughput and 1.09x energy efficiency gains over static schedules, and 1.44x throughput and 1.66x energy efficiency over GPU-only execution.
  • Faster interconnects such as PCIe 5.0 and CXL 3.0 change the optimal device allocation, so communication-cost modeling is essential, not optional, for the scheduler's decisions.
  • The balanced mode lets an operator cap throughput loss at 30% while minimizing energy, giving a concrete energy-performance trade-off when QoS targets exist.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The same dynamic-programming search should extend to more than two device types and to arbitrary DAG-shaped workloads, since the stage-grouping mechanism only assumes consecutive kernels can be fused and each device type has a performance estimator; the paper does not demonstrate this.
  • The small average sub-optimality loss suggests the schedule-quality landscape is fairly flat near the optimum, so cheap approximate performance models may be enough for online rescheduling; the paper does not test this flatness directly.
  • A testable extension not explored in the paper is online re-fitting of the linear regression models from measured kernel times as new data distributions arrive, which could maintain the 77/86 optimal-schedule rate on workloads that drift from the synthetic training profiles.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper introduces DyPE, a scheduling framework for heterogeneous systems with GPUs and FPGAs. DyPE takes a workload description, system specifications, kernel performance models, and design objectives as inputs, and uses a dynamic-programming scheduler to explore pipeline configurations under different objectives (performance-optimized, balanced, energy-optimized). Kernel execution times are estimated with linear regression models trained on synthetic profiles, with special formulas for sparse SpMM and sliding-window attention. The authors built a real testbed with two MI210 GPUs, three U280 FPGAs, and peer-to-peer FPGA-GPU transfers. They evaluate DyPE on GNN (GCN/GIN) and sliding-window transformer workloads across PCIe 4.0, PCIe 5.0, and CXL 3.0 interconnect assumptions. The headline claims are that DyPE finds the optimal schedule in 77/86 cases (77/84 in the body), that static scheduling is optimal in only 13/86 cases, that the average loss in sub-optimal cases is 3.95%, and that DyPE improves throughput by 1.53x and energy efficiency by 1.09x over a static baseline. The paper also reports that model inaccuracies rarely change the scheduling decision, with sub-optimality rates of 3/42 and 4/42 for throughput- and energy-optimized GNN cases.

Significance. The paper attacks a real problem: input-dependent sparsity and data characteristics can change which device mapping is best, and static or semi-static schedules cannot adapt. The hardware contribution is substantial: the authors built a working FPGA-GPU cluster with peer-to-peer transfers and validated schedules against actual measured kernel times. If the claims held, DyPE would be a valuable instance of data-aware scheduling for irregular workloads. The paper also shows a useful methodology point: evaluating a scheduler by comparing model-based decisions against decisions made with measured kernel timings is a step beyond validating the regression alone. However, the central optimality claim is not yet established: the DP formulation in Algorithm 1 does not have a guaranteed optimal-substructure property, and the experimental sections contain numeric inconsistencies between the abstract and the body. The significance of the contribution depends on fixing these load-bearing issues; the review therefore recommends major revision rather than acceptance.

major comments (3)
  1. [Section II-A, Algorithm 1 and Section VI-B]
  2. [Abstract, Section I, Section VI-B and Table III]
  3. [Section V and Section VI-B]
minor comments (5)
  1. [Section V, Equation (8)]
  2. [Section VI-C, Table IV]
  3. [Section VI-C, Figure 7]
  4. [Section VI-B]
  5. [Section II-A]

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: schedule quality is validated against measured kernel times and real-hardware throughput, not against the fitted model's own outputs.

full rationale

The derivation chain is not circular. Section V fits linear-regression kernel performance models to measured synthetic profiles, but these models are independent inputs to the scheduler; the paper does not define schedule quality in terms of the model. Section VI-B validates model accuracy by running the scheduler with actual measured kernel performance as the reference and counting how often the estimation-model schedule deviates from it. Although the sentence 'comparing the outcomes to the optimal schedules determined with the estimation model' is awkwardly worded, the surrounding text and Table III only make sense if the measured-performance run is the ground truth; a model-to-model comparison would make all cases optimal by construction and is not what is reported. The 77/86 claim is therefore not a fitted input renamed as a prediction. The DP search in Algorithm 1 is not proven to produce globally optimal schedules even with perfect fperf and fcomm, so the oracle used in Section VI-B has the same search-state limitations; this is a correctness and validation-strength concern, not an input-output circularity. The FleetRec* baseline is a constrained version of DyPE, which makes it a weak comparison, but the static and GPU-only baselines are independently implemented, and the central throughput and energy measurements are taken on real hardware. The only notable self-citation is [6] (SWAT), whose pipeline parameters tpipeline=201, tinit=904, and F=421MHz are used in Eq. (9); this is prior work by some of the same authors, but it supplies design constants for an FPGA attention accelerator, not the paper's optimality result, and the FPGA implementation is measurable. No step reduces to its own inputs by definition.

Assumptions & free parameters 5 free parameters · 5 assumptions · 0 invented entities

The central claim depends on empirical calibrations (regression coefficients and scaling factors) and on assumptions about communication and power behavior. The paper does not release fitted values or validation data, so the reader cannot independently inspect how much of the result follows from tuning.

free parameters (5)
  • SpMM FPGA scaling factor C = not reported
    Multiplying the Sextans analytical model in Eq. (V): t = C*(nnz+13M)N/(F*NM)*1e3. C is trained on synthetic benchmark data; no value or training set reported.
  • SpMM GPU regression coefficients C1-C4 = not reported
    Eq. (7): t = C1*N + C2*nnz + C3*GFLOP + C4*arm. Coefficients fit to generated data; no values, error, or cross-validation reported.
  • GEMM GPU regression coefficients C1-C6 = not reported
    Eq. (8) lists C1 through C5 with C5 repeated, presumably six coefficients fit to data; no values or validation reported.
  • Sliding-window FPGA scaling factor C = not reported
    Eq. (9) scales the SWAT model (tpipeline=201, tinit=904, F=421MHz) by a fit coefficient C; no value reported.
  • Balanced mode throughput floor = 70% of performance-optimized throughput
    Design choice in Section II.A that defines the balanced mode and shapes reported energy/throughput trade-offs; not derived.
assumptions (5)
  • domain assumption Kernel execution time is a smooth, low-dimensional function of NNZ, dimensions, GFLOP, and arithmetic intensity, so a linear regression on synthetic samples predicts real-kernel runtimes.
    Section V, Equations 7-9: all four performance formulas are regressions or scaled analytical fits over these features.
  • domain assumption The communication cost model, including the one-cycle CPU-FPGA delay to separate FPGA-GPU transfers, captures PCIe contention accurately.
    Section II-B and Figure 4: the conflict avoidance delay is a modeling choice, not verified by independent measurements.
  • domain assumption Power draw during execution, transfer, and idle states measured with XRT/ROCm is stable and additive across devices.
    Section VI-A: energy efficiency numbers depend on this additivity assumption; no variance or calibration details are reported.
  • domain assumption The manually tuned static baseline and the FleetRec* constraint implementation fairly represent conventional static scheduling.
    Section VI-A: FleetRec* is implemented by adding design constraints to DyPE, not the original FleetRec artifact.
  • domain assumption Projected PCIe5/CXL3 interconnect data transfer times are valid proxies for real hardware behavior.
    Section VI-A: only data transfer time is projected while compute times are measured on PCIe4 hardware.

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Cite this review

Pith. "Pith review of Data-aware Dynamic Execution of Irregular Workloads on Heterogeneous Systems." pith.science (2026). https://pith.science/paper/6RXVXHRJ

@misc{pith2026250206304,
  author       = {Pith},
  title        = {Pith review of: Data-aware Dynamic Execution of Irregular Workloads on Heterogeneous Systems},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/6RXVXHRJ}},
  note         = {Machine review of arXiv:2502.06304}
}
read the original abstract

Current approaches to scheduling workloads on heterogeneous systems with specialized accelerators often rely on manual partitioning, offloading tasks with specific compute patterns to accelerators. This method requires extensive experimentation and human effort to identify the tasks suitable for the accelerator. To solve this problem, we introduce DyPe, a scheduling framework tailored for heterogeneous systems with specialized accelerators. Our method automatically partitions, deploys, and reschedules execution when necessary by dynamically analyzing the characteristics of the input data and leveraging the interoperator parallelism among heterogeneous devices. DyPe navigates a multi-objective, multi-constraint design space that considers both system constraints and application requirements, which allows it to discover Pareto-optimal mapping configurations, improving the system's overall performance and effectively managing energy-performance trade-offs. To demonstrate the benefits of our approach on real hardware, we build a heterogeneous system of GPUs and FPGAs with peer-to-peer data transfers. The experiments show that conventional static scheduling is optimal for 13 out of 86 cases for different workloads and system settings while DyPe is adaptable and able to find the optimal schedule in 77 out of 86 cases, with an average of only 3.95% performance or energy efficiency loss in the sub-optimal cases. Performance evaluation of DyPe shows an average of 1.53x throughput and 1.09x energy efficiency improvement over the static schedule baseline and 1.44x throughput and 1.66x energy efficiency over the GPU-only baseline.

Figures

Figures reproduced from arXiv: 2502.06304 by the authors.

Figure 1
Figure 1. Different parallelism patterns. As a concrete example, our experiment shows that three AMD ALVEO™ U280 FPGAs can deliver performance com￾parable to that of one AMD Instinct™ MI210 GPU when running the Sparse Matrix-Matrix Multiplication (SpMM) kernel with high sparsity level, achieving 1.6x greater energy efficiency than the GPU. Notably, this energy efficiency ad￾vantage of FPGAs over GPUs increases as the sparsity… view at source ↗
Figure 2
Figure 2. Example pipelined schedules for GCN inference. (a) 2-stages [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. The D [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figures from the paper (6 more)
Figure 4
Figure 4. Figure 4: Example 2-stages pipeline with and without conflict. [PITH_FULL_IMAGE:figures/full_fig_p004_4.png]
Figure 5
Figure 5. Figure 5: System hardware 101 102 103 104 105 106 number of bytes transferred 5 10 15 20 25 30 P2P speedup FPGA->GPU GPU->FPGA 2x [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]
Figure 6
Figure 6. Figure 6: Data transfer speedup with P2P direct data transfer. [PITH_FULL_IMAGE:figures/full_fig_p005_6.png]
Figure 7
Figure 7. Figure 7: Througput and energy efficiency comparison between D [PITH_FULL_IMAGE:figures/full_fig_p009_7.png]
Figure 8
Figure 8. Figure 8: Throughput and energy efficiency gain of D [PITH_FULL_IMAGE:figures/full_fig_p009_8.png]
Figure 9
Figure 9. Figure 9: Design space exploration on GCN-S1 and GCN-OP, evaluated [PITH_FULL_IMAGE:figures/full_fig_p010_9.png]

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Pith tools

Reviewed August 8, 2026 · model on record in the stance chip above.